LMK05028RGCT datasheet(7/94 Pages) TI2

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5 Specifications

5.1 Absolute Maximum Ratings

Over operating free-air temperature range (unless otherwise noted)(1)

MIN

MAX

UNIT

VDD(2)

Core supply voltages

-0.3

3.6

VDDO(3)

Output supply voltages

-0.3

3.6

VIN

Input voltage range for clock and logic inputs

-0.3

VDD+0.3

VOUT_LOGIC

Output voltage range for logic outputs

-0.3

VDD+0.3

VOUT

Output voltage range for clock outputs

-0.3

VDDO+0.3

Junction temperature

150

°C

Tstg

Storage temperature range

-65

150

°C

(1)

Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply

functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.

If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully

functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.

(2)

VDD refers to all core supply pins or voltages. All VDD core supplies must be powered-on before the PDN is pulled high to trigger the

internal power-on reset (POR).

(3)

VDDO refers to all output supply pins or voltages. VDDO_x refers to the output supply for a specific output channel, where x denotes

the channel index.

5.2 ESD Ratings

VALUE

UNIT

V(ESD)

Electrostatic

discharge

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1)

±2000

Charged device model (CDM), per JEDEC specification JESD22-C101, all

pins(2)

±750

(1)

JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2)

JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

5.3 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted)

MIN

NOM

MAX

UNIT

VDD(1)

Core supply voltages

3.135

3.3

3.465

VDDO_x(2)

Output supply voltage for AC-LVDS/CML/LVPECL or HCSL driver

1.71

1.8, 2.5, 3.3

3.465

VDDO_x(2)

Output supply voltage for 1.8-V LVCMOS driver(3)

1.71

1.8

1.89

VDDO_x(2)

Output supply voltage for 2.5-V LVCMOS driver(3)

2.375

2.5

2.625

VIN

Input voltage range for clock and logic inputs

3.465

Junction temperature

135

°C

tVDD

Power supply ramp time(4)

0.01

100

nEEcyc

EEPROM program cycles(6)

100

cycles

SROUT

Output slew rate mode(5)

Fast

(1)

VDD refers to all core supply pins or voltages. All VDD core supplies must be powered-on before internal power-on reset (POR).

(2)

VDDO refers to all output supply pins or voltages. VDDO_x refers to the output supply for a specific output channel, where x denotes

the channel index.

(3)

The LVCMOS driver supports full rail-to-rail swing when VDDO_x is 1.8 V or 2.5 V ±5%. When VDDO_x is 3.3 V, the LVCMOS driver

does not fully swing to the positive rail due to the dropout voltage of the output channel's internal LDO regulator.

(4)

Time for VDD to ramp monotonically above 2.7 V for proper internal power-on reset. For slower or non-monotonic VDD ramp, hold

PDN low until after VDD voltages are valid.

(5)

Clock output characteristics are specified for all driver types with the output slew rate mode programmed to Fast. Some specifications

cannot be met with the output slew rate programmed to Nominal.

(6)

nEEcyc specifies the maximum EEPROM program cycles allowed for customer programming. The initial count of factory-programmed

cycles is non-zero due to production tests, but factory-programmed cycles are excluded from the nEEcyc limit. The total number of

EEPROM program cycles can be read from the 8-bit NVM count status register (NVMCNT), which automatically increments by 1 on

each successful programming cycle. TI does not ensure EEPROM endurance if the nEEcyc limit is exceeded by the customer.

www.ti.com

LMK05028

SNAS724B – FEBRUARY 2018 – REVISED FEBRUARY 2025

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