LMK05028RGCT datasheet(22/94 Pages) TI2

22 / 94 page

7.2.1 PLL Architecture Overview

Figure 7-3 shows the 3-loop architecture implemented the same for both PLL channels with exception of the

VCO frequency range. Each channel has three phase-locked loops with two digital PLLs (REF-DPLL and TCXO-

DPLL) and one analog PLL (APLL) with integrated VCO. The REF-DPLL and TCXO-DPLL are each comprised

of a time-to-digital converter (TDC), digital loop filter (DLF), feedback prescaler (PR), and 40-bit fractional

feedback (FB) divider with sigma-delta-modulator (SDM or "MASH"). The APLL is comprised of a reference

frequency doubler (×2), phase-frequency detector (PFD), loop filter (LF), fractional feedback (N) divider with

SDM, and VCO.

PLLx Channel

REF-DPLL

TDC

TCXO-DPLL

TDC

APLL

PFD

×2

÷R

16-bit

(x6)

VCO

IN0

IN1

IN2

IN3

VCO1 FB

VCO2 FB

Cascaded PLL

option

(3)

VCOx FB

Post

Dividers

0 1 2

÷P1

÷P2

TCXO Mux

DCO option

(2)

DCO loop select

DCO

FDEV

×2

÷M

TCXO

DPLL feedback clock

38-bit

REF Mux

÷FB

40-bit Frac-N SDM

÷FB

40-bit Frac-N SDM

÷N

40-bit Frac-N SDM

VCO1: 4.8 to 5.4 GHz

VCO2: 5.5 to 6.2 GHz

5-bit

fREF-TDC

fTCXO-TDC

fPD

DLF

Loopback

Dividers

VCO1 FB

VCO2 FB

Output

Muxes

fVCO/P1

fVCO/P2

FINC/FDEC

fVCO

÷PR

SDM control

(1)

/4 to /9,

/11, /13

/2 to /17

Fractional divider SDM control node depends on the selected PLL mode configuration.

DCO frequency adjustments can be software or pin controlled.

PLL cascading options: a) PLL1 VCO1 Loopback to PLL2, b) PLL2 VCO2 Loopback to PLL1.

Figure 7-3. PLL Architecture (One Channel)

Table 7-1 summarizes the PLL mode configuration options available in each channel. These modes support

a wide range of use cases depending to the clock functionality and performance required in the application.

Most applications uses 2-loop REF-DPLL or 3-loop mode for network synchronization clock features such as

programmable loop bandwidth for jitter and wander attenuation, hitless switching, precise digital holdover, DCO

frequency steering, or zero delay mode.

Table 7-1. PLL Mode Configuration Options

PLL MODE

FRACTIONAL SDM ENABLED (SDM CONTROL FROM)

DCO MODE OPTION

FREE-RUN /

HOLDOVER CLOCK

REF-DPLL

TCXO-DPLL

APLL

1-Loop (APLL only)

–

Y (Free-run from XO)

–

2-Loop REF-DPLL

Y (DCO option)

–

Y (REF-DPLL)

REF-DPLL SDM

2-Loop TCXO-DPLL

–

Y (DCO option)

Y (TCXO-DPLL)

TCXO-DPLL SDM

TCXO

3-Loop

Y (DCO option)

Y (REF-DPLL)

Y (TCXO-DPLL)

REF-DPLL SDM

TCXO

The following sections describe the basic principle of operation for 2-loop and 3-loop modes. See PLL Operating

Modes for more details on the PLL modes of operation including holdover.

7.2.2 3-Loop Mode

In 3-loop mode, the TCXO/OCXO source determines the free-run and holdover frequency stability and accuracy,

and the XO source determines the output phase noise and jitter performance over the 12-kHz to 20-MHz

LMK05028

SNAS724B – FEBRUARY 2018 – REVISED FEBRUARY 2025

www.ti.com

Submit Document Feedback

Product Folder Links: LMK05028

LMK05028RGCT bảng dữ liệu(PDF) 22 Page - Texas Instruments

LMK05028RGCT bảng dữ liệu(HTML) 22 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94

bảng dữ liệu tải về

Link URL