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DP83867CS bảng dữ liệu(PDF) 109 Page - Texas Instruments

tên linh kiện DP83867CS
Giải thích chi tiết về linh kiện  DP83867E/IS/CS Robust, High Immunity, Small Form Factor 10/100/1000 Ethernet Physical Layer Transceiver
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DP83867CS bảng dữ liệu(HTML) 109 Page - Texas Instruments

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8.2.1.4 Clock Out (CLK_OUT) Phase Noise
Figure 8-6 provides a phase noise plot for the 25MHz clock output from the device.
A.
This measurement was taken on a DP83867 configured as a slave. The PHY was linked to another DP83867 configured as the master.
Both devices had PRBS enabled (BISCR, register 0x0016, configured to 0xD000).
B.
The phase noise on the CLK_OUT pin before linkup and after link up with no packets being generated are expected to be lower than
pictured.
Figure 8-6. 25MHz Clock Output Phase Noise
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DP83867CS, DP83867IS, DP83867E
SNLS504F – OCTOBER 2015 – REVISED JANUARY 2025
Copyright © 2025 Texas Instruments Incorporated
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Product Folder Links: DP83867CS DP83867IS DP83867E



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