DP83867CS datasheet(37/129 Pages) TI2

37 / 129 page

MDI MODE

MIRROR PORT CONFIGURATION

MDI or MDIX

A → D

B → C

C → B

D → A

Mirror mode can be enabled through strap or through register configuration using the Port Mirror Enable bit in

the CFG4 register (address 0x0031). In Mirror mode, the polarity of the signals is also reversed.

7.4.6.6 Interrupt

The DP83867 can be configured to generate an interrupt when changes of internal status occur. The interrupt

allows a MAC to act upon the status in the PHY without polling the PHY registers. The interrupt source can be

selected through the interrupt registers, MICR (register address 0x0012) and ISR (register address 0x0013).

7.4.6.7 IEEE 802.3 Test Modes

IEEE 802.3 specification for 1000BASE-T requires that the PHY layer be able to generate certain well defined

test patterns on TX outputs. Clause 40 section 40.6.1.1.2 Test Modes describes these tests in detail. There are

four test modes as well as the normal operation mode. These modes can be selected by writing to the CFG1

See IEEE 802.3 section 40.6.1.1.2 Test modes for more information on the nature of the test modes. The

DP83867 provides a test clock synchronous to the IEEE test patterns. The test patterns are output on the MDI

pins of the device and the transmit clock is output on the CLK_OUT pin.

For more information about configuring the DP83867 for IEEE 802.3 compliance testing, see the How to

Configure DP838XX for Ethernet Compliance Testing application report (SNLS239).

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DP83867CS, DP83867IS, DP83867E

SNLS504F – OCTOBER 2015 – REVISED JANUARY 2025

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