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DP83867CS bảng dữ liệu(PDF) 97 Page - Texas Instruments

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Giải thích chi tiết về linh kiện  DP83867E/IS/CS Robust, High Immunity, Small Form Factor 10/100/1000 Ethernet Physical Layer Transceiver
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7.6.106 TDR General Configuration Register 1 (TDR_GEN_CFG1)
Table 7-116. TDR General Configuration Register 1 (TDR_GEN_CFG1), Address 0x0180
BIT
BIT NAME
DEFAULT
DESCRIPTION
15:13
RESERVED
0, RO
RESERVED
12
TDR_CH_CD_BYPASS
0, RW
TDR Bypass for Channel C and D:
1 = Bypass channel C and D in TDR tests.
0 = Normal operation.
11
TDR_CROSS_MODE_DIS
0, RW
Disable TDR Cross Mode:
1 = Disable cross mode option. Do not check cross channels. Only
listen to the channel being used for transmit.
0 = Normal operation.
10
TDR_NLP_CHECK
1, RW
TDR NLP Check:
1 = Check for NLPs during silence.
0 = Normal operation.
9:7
TDR_AVG_NUM
110, RW
Number Of TDR Cycles to Average:
111: RESERVED: Writes ignored, read as 0.
110: 64 TDR cycles
101: 32 TDR cycles
100: 16 TDR cycles
011: 8 TDR cycles
010: 4 TDR cycles
001: 2 TDR cycles
000: 1 TDR cycle
6:4
TDR_SEG_NUM
101, RW
Set the number of TDR segments to check.
3:0
TDR_CYCLE_TIME
010, RW
Set the time for each TDR cycle. Value is measured in
microseconds.
7.6.107 TDR Peak Locations Register 1 (TDR_PEAKS_LOC_1)
Table 7-117. TDR Peak Locations Register 1 (TDR_PEAKS_LOC_1), Address 0x0190
BIT
BIT NAME
DEFAULT
DESCRIPTION
15:8
TDR_PEAKS_LOC_A_1
0, RO
Location of the second peak discovered by the TDR mechanism on
channel A. The value of these bits is translated into distance from the
PHY.
7:0
TDR_PEAKS_LOC_A_0
0, RO
Location of the first peak discovered by the TDR mechanism on
channel A. The value of these bits is translated into distance from the
PHY.
7.6.108 TDR Peak Locations Register 2 (TDR_PEAKS_LOC_2)
Table 7-118. TDR Peak Locations Register 2 (TDR_PEAKS_LOC_2), Address 0x0191
BIT
BIT NAME
DEFAULT
DESCRIPTION
15:8
TDR_PEAKS_LOC_A_3
0, RO
Location of the fourth peak discovered by the TDR mechanism on
channel A. The value of these bits is translated into distance from the
PHY.
7:0
TDR_PEAKS_LOC_A_2
0, RO
Location of the third peak discovered by the TDR mechanism on
channel A. The value of these bits is translated into distance from the
PHY.
7.6.109 TDR Peak Locations Register 3 (TDR_PEAKS_LOC_3)
Table 7-119. TDR Peak Locations Register 3 (TDR_PEAKS_LOC_3), Address 0x0192
BIT
BIT NAME
DEFAULT
DESCRIPTION
15:8
TDR_PEAKS_LOC_B_0
0, RO
Location of the first peak discovered by the TDR mechanism on
channel B. The value of these bits is translated into distance from the
PHY.
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DP83867CS, DP83867IS, DP83867E
SNLS504F – OCTOBER 2015 – REVISED JANUARY 2025
Copyright © 2025 Texas Instruments Incorporated
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Product Folder Links: DP83867CS DP83867IS DP83867E



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