STPM098C datasheet(87/110 Pages) STMICROELECTRONICS

87 / 110 page

Figure 73. DPS timing diagram

PHASE2_ADD

PHASE2_DROP

PHASE3_ADD

PHASE3_DROP

PHASE4_ADD

PHASE4_DROP

(ISENj−CFILT/VREF1)

j=1

PHASE5_ADD

PHASE5_DROP

IPHASE5 status

IPHASE4 status

IPHASE3 status

IPHASE2 status

IPHASE1 status

PWM5 HIZ

PWM4 ACTIVE

PWM3 ACTIVE

PWM4 ACTIVE

PWM1 ACTIVE

PWM4 HIZ

PWM3 HIZ

PWM2 HIZ

PWM4 HIZ

PWM3 HIZ

PWM2 HIZ

When DPS is active, a minimum number of active phases can be configured through a dedicated PMBus™

command as follows:

Table 68. DPS minimum phase drop limit configuration bits

NPH_PS02

NPH_PS01

NPH_PS00

Description

At least 1 active phase (default)

At least 1 active phase

At least 2 active phases

At least 3 active phases

At least 4 active phases

At least 5 active phases

At least 6 active phases

At least 7 active phases

DPS minimum phase number (NPH_PS) should be always lower than or equal to the phase number assigned to

the loop (PHASE_CFG).

In case DPS minimum phase number is set higher than the assigned phase number, the NPH_PS configuration

has the higher priority in defining the number of active phases.

Example: if NPH_PS = 0x4 for loop 1 while PHASE_CFG = 0x2, then loop 1 will have 4 active phases instead of

During fast load increase DPS control is overridden to quickly support the current change. The DCO output period

is monitored and if it falls below an adaptive threshold the controller instantly increases the number of active

phases.

TDCO≤ 1N+1TNOMINALoccurs,theactivephasenumberoftheloopisincreasedby1,independentlyoftheDPS

assertion.

STPM098C

Functional description

DS14440 - Rev 1

page 87/110

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