L99PM72PXP datasheet(116/128 Pages) STMICROELECTRONICS

116 / 128 page

ST SPI

L99PM72PXP

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Doc ID 023553 Rev 3

6.2.22

Global status register

The Global Error Flag is set once the watchdog failure counter (SR3<7:4>) is unequal to 0

(see also Section 2.5: Fail Safe Mode).

Table 132.

Global status register

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Hex

value

Active high/low

High

Low

High

Default value in Normal Mode - after

correct WD trigger or after Read & Clear

on Error Flags

001

000

Power ON

100

000

Power ON weak battery (7)

100

000

Communication error

VS overvoltage or undervoltage

WD failure

101

000

SPI Error (DI Stuck)

101

000

TSD1

101

010

TSD2

101

110

V1 Fail

101

001

Other Device Failure(8)

101

000

The following Status Bits are reported in the Global Error Flag:

Global Status Register: Bits 6-0

Status Register 1: Bits 10-0

Status Register 3: Bits 15, 11, 7-2

Communication Error: invalid number of CLOCK cycles during CSN low or failed parity check on standby command.

Cleared with CLR command on SR3.

Cleared with “READ and CLEAR” on SR3 (-> TSD1)

Diagnosis bit only, VS Fail is not a Fail-Safe event; cleared by Read&Clear. Bit is automatically cleared at (VS >VSUV) and

(VS < VSOV) if Vlock_out_en = 0

Cleared with a valid WD trigger (WD fail) or by clearing the corresponding status register related to failure

Slow VS ramp-up (VS undervoltage is filtered with 64µs after power-on reset)

The Global Error Flag is raised due to a failure condition which is not reported in the Global Status Register. The Failure is

reported in the Status Registers 1-5

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