L9800 datasheet(42/55 Pages) STMICROELECTRONICS

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11.4

Electrical parameters

Table 17. SPI electrical parameters

Symbol

Description

Test condition

Min.

Typ.

Max.

Unit

Input SPI pin characteristics–low level

VNCS(L) NCS

0.8

VSCLK(L) CLK

0.8

VSI(L)

0.8

Input SPI pin characteristics–high level

VNCS(H) NCS

VSCLK(H) SCLK

VSI(H)

Input pull-up resistor at NCS pin

RNCS

Input pull-up resistor at NCS pin

NCS = 0.8V

100

kΩ

Input pull-down resistor at pin SCLK, SI

RSCLK

Input pull-down resistor on SCLK

VSCLK = 2 V

180

kΩ

RSI

Input pull-down resistor on SI

VSI = 2 V

180

kΩ

Output characteristic

VSO(L)

L level output voltage

ISO = -1.5 mA

0.4

VSO(H)

H level output voltage

ISO = 1.5 mA

VDDI

O -

0.4

VDDI

ISO(OFF) Output tristate leakage current

VNCS = VDDIO, VBATTO = 0 V

-1

μA

ISO(OFF) Output tristate leakage current

VNCS = VDDIO,

VBATTO = VDDIO

-1

μA

Timings

tNCS(lead) Enable lead time (falling NCS to rising CLK)

VDDIO = 4.5 V or VBATT > 7 V

200

tNCS(lag) Enable lag time (falling CLK to rising NCS)

VDDIO = 4.5 V or VBATT > 7 V

200

tNCS(td) Transfer delay time (rising NCS to falling NCS)

VDDIO = 4.5 V or VBATT > 7 V

650

tSO(en)

Output enable time (falling NCS to SO valid)

VDDIO = 4.5 V or VBATT > 7 V,

CL = 20 pF at MISO pin

200

tSO(dis)

Output disable time (rising NCS to SO tristate)

VDDIO = 4.5 V or VBATT > 7 V,

CL = 20 pF at MISO pin

200

fSCLK

Serial clock frequency

VDDIO = 4.5 V or VBATT > 7 V

MHz

tSCLK(H) Serial clock “high” time

VDDIO = 4.5 V or VBATT > 7 V

tSCLK(L) Serial clock “low” time

VDDIO = 4.5 V or VBATT > 7 V

tSI(su)

Data setup time (required time MOSI to rising

CLK)

VDDIO = 4.5 V or VBATT > 7 V

tSI(h)

Data hold time (rising CLK to SI)

VDDIO = 4.5 V or VBATT > 7 V

L9800

Serial peripheral interface (SPI)

DS14041 - Rev 2

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