L9800 datasheet(22/55 Pages) STMICROELECTRONICS

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6.1.9

Low operating power-on VDDIO

When the VDDIO supply voltage drops in the range indicated by VDDIO(UV), the bit STA_1.VDDIO_UV is set to

“1”. This is valid if the digital NPOR is ‘1’. For all conditions that generate an NPOR = 0, a dedicated clear on read

STA_1. NPOR bit is set. As soon as VDDIO overcomes the minimum of the voltage operative threshold

VDDIO(UV_RECOVERY) the bit STA_1.VDDIO_UV is set to “0” after the first clear on read.

One of the following conditions generates the NPOR condition (reset of the whole internal logic):

1. General internal supply failure (internal 3.3 V supply in UV or bandgap reference not correct)

2. VDDIO < VDDIO(UV) AND IN1 = 0 AND IN0 = 0

6.1.10

Power-down

The power-down condition is satisfied if both supply voltages undergo 3 V or, if at least one of them is applied to

the device in its operative range, the INn and IDLE pins are all set to “low”. If one or more channels are switched

on before power-down, it is necessary to assert a reset to ensure a correct turn-off timing. All possible power-

down scenarios are described here below:

Figure 14. Scenario 1 power-down

VBATT

VDDIO

IDLE

POR

V3V3

V1V2

Scenario 1: power-down with both supplies dropping together under 3 V. Although IDLE is high internal supply

reference and vbg drop; POR is set to zero. IN0 = IN1 = 0 V.

Figure 15. Scenario 2 power-down

VBATT

VDDIO

IN0

POR

V3V3

V1V2

Scenario 2: power-down with both supplies dropping together under 3 V. Although IN0 is high internal supply

reference and vbg drop; POR is set to zero. IDLE = IN1 = 0 V.

L9800

Power supply

DS14041 - Rev 2

page 22/55

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