L9800 datasheet(21/55 Pages) STMICROELECTRONICS

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Figure 13. Transition time diagram

Limp-home mode

Sleep mode

Idle mode

tIDLE2SLEEP

tACTIVE2SLEEP

tSLEEP2IDLE

tIDLE2ACTIVE

tACTIVE2IDLE

LH2ACTIVE

tACTIVE2LH

tLH2SLEEP

tSLEEP2LH

Active mode

6.1.7

Reset

The following four conditions reset the SPI register (r/w) to the default value:

1. VDDIO is not present or below the minimum value of VDDIO(UV)

2. IDLE pin is set to “low” with both INn “low"

3. A reset command (CFG_1.RST set to “1”) is executed

4. NRES pin asserted

DIAG_OVC_OVT bits are not cleared by a reset command (for functional safety).

STA_1.VDDIO_UV and STA_1.VBATT_UV bits are not cleared by a reset command (for functional safety).

In particular, all channels are switched OFF (if there are no input pin set to “high”) and the input mapping

configuration is reset.

6.1.8

Undervoltage on VBATT

If the device is operative and the supply voltage drops below VBATT(UV_L), the logic sets the bit

STA_1.VBATT_UV to “1”. As soon as the supply voltage VBATT is above VBATT(UV_H), the bit STA_1.VBATT_UV

is set back to “0” after the first clear on read.

Undervoltage condition on VBATT may influence the status of the channels according to VS_UV_MASK bit

status, as described in the Table 18.

L9800

Power supply

DS14041 - Rev 2

page 21/55

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