L9800 datasheet(41/55 Pages) STMICROELECTRONICS

tên linh kiện	L9800

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Figure 31. Daisy chain

GADG081120231031GT

Device 1

Device 3

Device 2

MCSN

MCLK

SPI

In the SPI block of each device, there is one shift register where each bit from the MOSI line is shifted in each

CLK. The bit shifted out occurs at the MISO pin. After 16 CLK cycles, the data transfer for one device is finished.

In single chip configuration, the NCS line must turn “high” to make the device acknowledge the transferred data.

In daisy chain configuration, the data shifted out at device 1 has been shifted into device 2. When using three

devices in daisy chain, more than 16 bits have to be shifted through the devices (depending on how many devices

are connected and how many SPI bits they have). After that, the MNCS line must turn “high” (see the Figure 32).

Figure 32. Data transfer in daisy chain

MNCS

MCLK

SI device 3

SI device 2

SI device 1

SO device 3

SO device 2 SO device 1

11.3

Timing diagrams

Figure 33. Timing diagram

L9800

Serial peripheral interface (SPI)

DS14041 - Rev 2

page 41/55

L9800 bảng dữ liệu(PDF) 41 Page - STMicroelectronics