L9678P datasheet(139/215 Pages) STMICROELECTRONICS

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DS11626 Rev 9

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L9678P, L9678P-S

Watchdog timer

214

8.1.1

Watchdog timer configuration

The watchdog timer can be configured on two different frequency modes:



Fast watchdog with maximum range of 2 ms and a resolution of 8 µs;



Slow watchdog with maximum range of 16.3 ms and a resolution of 64 µs.

The watchdog window times are SPI programmable. The configuration of watchdog timer

frequency and window times can be done by setting the Watchdog Timer Configuration

when the device is in the Init operating state, as shown in Figure 9. As soon as the Diag

state is entered, the watchdog control is enabled and the watchdog configuration is fixed

and cannot be changed anymore.

8.1.2

Watchdog timer operation

While in the WD1_INITIAL state, watchdog service must begin or a SPI command with

WD1_TOVR=1 must be received within the first 500 ms. If the WD1 timer override bit is set,

the device can stay in the WD1_INITIAL state indefinitely without watchdog service.

To refresh WD1, the logic must receive a Watchdog Timer Register (WD1T) SPI command

containing the expected key value within the WD1 time window (WDTMIN+WDTDELTA). If it

is received too early or too late the WD1_ERROR signal will be asserted. The

WD1_ERROR will not be asserted in case a SPI command containing the Watchdog Timer

(WDTMIN+WDTDELTA). This allows the system software to repeatedly transmit the key

value until it needs to change to the correct key value.

Upon reception of the correct key value within the window, the logic will reset the watchdog

timer to create a new window.

The timer is cleared upon writing code 'A' and code 'B' (either in 'A' - 'B' or 'B' - 'A'

sequences) to the WD1CTL[1:0] bits, in the WD1T register. The watchdog timer value can

be read via the WD1T register.

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