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L9396 bảng dữ liệu(PDF) 86 Page - STMicroelectronics |
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L9396 bảng dữ liệu(HTML) 86 Page - STMicroelectronics |
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86 / 109 page  System functional safety implementations L9396 86/109 DS12539 Rev 10 BOOST OT FAILSAFE FAULT MASKED FAILSAFE FAULT FAILSAFE FAULT BUCK OT FAILSAFE FAULT MASKED FAILSAFE FAULT FAILSAFE FAULT VCC OT FAILSAFE FAULT MASKED FAILSAFE FAULT FAILSAFE FAULT CP OT FAILSAFE FAULT MASKED FAILSAFE FAULT FAILSAFE FAULT VCC UV/OV FAILSAFE FAULT FAILSAFE FAULT MASKED FAILSAFE FAULT VCORE UV/OV FAILSAFE FAULT FAILSAFE FAULT MASKED FAILSAFE FAULT VCC5 UV/OV FAILSAFE FAULT FAILSAFE FAULT MASKED FAILSAFE FAULT SPI ERROR FAILSAFE FAULT FAILSAFE FAULT FAILSAFE FAULT FAILSAFE FAULT Table 56. Masking bits and fault sources (continued) - FAILSAFE / FAULT OUTPUT WD1 and WD2 FAULT MASK FAILSAFE / FAULT OUTPUT THERMAL WARNING MASK FAILSAFE / FAULT OUTPUT µC VOLTAGE FAULT MASK FAILSAFE / FAULT OUTPUT BOOST FAULT MASK Table 57. Fail safe output Symbol Parameter Conditions/Comments Min. Typ. Max. Unit VOL FSN Logic Output Low Voltage 5 kΩ tied to VCC - - 0.4 V VOH FSN Logic Output High Voltage 5 kΩ tied to VCC VCC- 0.05 - - V tr Rise time Load = 50 pF; 20%-80% - - 1 µs tf Fall time Load = 50 pF; 20%-80% - - 1 µs Ileak_FSN FSN leakage current FSN output off 0 < FSN < VCC -2 - 2 µA TFSN_DELAY FSN digital assertion delay Guaranteed by scan, ADV_CONFIG[7:9]=000 0 mS TFSN_DELAY FSN digital assertion delay Guaranteed by scan, ADV_CONFIG[7:9]=001 0 - 2 mS TFSN_DELAY FSN digital assertion delay Guaranteed by scan, ADV_CONFIG[7:9]=010 2 - 4 mS TFSN_DELAY FSN digital assertion delay Guaranteed by scan, ADV_CONFIG[7:9]=011 6 - 8 mS TFSN_DELAY FSN digital assertion delay Guaranteed by scan, ADV_CONFIG[7:9]=100 8 - 10 mS TFSN_DELAY FSN digital assertion delay Guaranteed by scan, ADV_CONFIG[7:9]=101 28 - 30 mS TFSN_DELAY FSN digital assertion delay Guaranteed by scan, ADV_CONFIG[7:9]=110 48 - 50 mS TFSN_DELAY FSN digital assertion delay Guaranteed by scan, ADV_CONFIG[7:9]=111 98 - 100 mS |
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