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STM32G030F6 bảng dữ liệu(PDF) 41 Page - STMicroelectronics |
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STM32G030F6 bảng dữ liệu(HTML) 41 Page - STMicroelectronics |
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41 / 94 page ![]() DS12991 Rev 1 41/94 STM32G030x6/x8 Electrical characteristics 80 5.3 Operating conditions 5.3.1 General operating conditions 5.3.2 Operating conditions at power-up / power-down The parameters given in Table 22 are derived from tests performed under the ambient temperature condition summarized in Table 21. 5.3.3 Embedded reset and power control block characteristics The parameters given in Table 23 are derived from tests performed under the ambient temperature conditions summarized in Table 21. Table 21. General operating conditions Symbol Parameter Conditions Min Max Unit fHCLK Internal AHB clock frequency - 0 64 MHz fPCLK Internal APB clock frequency - 0 64 VDD/DDA Supply voltage - 2.0(1) 3.6 V VBAT Backup operating voltage - 1.55 3.6 V VIN I/O input voltage - -0.3 Min(VDD + 3.6, 5.5)(2) V TA Ambient temperature(3) Suffix 6(4) -40 85 °C TJ Junction temperature Suffix 6(4) -40 105 °C 1. When RESET is released functionality is guaranteed down to VPDR min. 2. For operation with voltage higher than VDD +0.3 V, the internal pull-up and pull-down resistors must be disabled. 3. The TA(max) applies to PD(max). At PD < PD(max) the ambient temperature is allowed to go higher than TA(max) provided that the junction temperature TJ does not exceed TJ(max). Refer to Section 6.5: Thermal characteristics. 4. Temperature range digit in the order code. See Section 7: Ordering information. Table 22. Operating conditions at power-up / power-down Symbol Parameter Conditions Min Max Unit tVDD VDD slew rate VDD rising - ∞ µs/V VDD falling 10 ∞ Table 23. Embedded reset and power control block characteristics Symbol Parameter Conditions(1) Min Typ Max Unit tRSTTEMPO(2) POR temporization when VDD crosses VPOR VDD rising - 250 400 μs VPOR(2) Power-on reset threshold - 2.06 2.10 2.14 V VPDR(2) Power-down reset threshold - 1.96 2.00 2.04 V |
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