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TMS320DM355 bảng dữ liệu(PDF) 1 Page - Texas Instruments

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tên linh kiện TMS320DM355
Giải thích chi tiết về linh kiện  Digital Media System-on-Chip (DMSoC)
PDF  154 Pages
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nhà sản xuất  TI [Texas Instruments]
Trang chủ  http://www.ti.com
Logo TI - Texas Instruments

TMS320DM355 bảng dữ liệu(HTML) 1 Page - Texas Instruments

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1
TMS320DM355 Digital Media System-on-Chip (DMSoC)
1.1 Features
TMS320DM355
Digital Media System-on-Chip (DMSoC)
SPRS463D – SEPTEMBER 2007 – REVISED FEBRUARY 2008
• 8-/16-bit YCC and Up to 18-Bit RGB666
• High-Performance Digital Media
Digital Output
System-on-Chip
• BT.601/BT.656 Digital YCbCr 4:2:2
–
216- and 270-MHz ARM926EJ-S Clock Rate
(8-/16-Bit) Interface
–
Fully Software-Compatible With ARM9
• Supports digital HDTV (720p/1080i)
• ARM926EJ-S Core
output for connection to external
–
Support for 32-Bit and 16-Bit (Thumb Mode)
encoder
Instruction Sets
• External Memory Interfaces (EMIFs)
–
DSP Instruction Extensions and Single
–
DDR2 and mDDR SDRAM 16-bit wide EMIF
Cycle MAC
With 256 MByte Address Space (1.8-V I/O)
–
ARM Jazelle Technology
–
Asynchronous16-/8-bit Wide EMIF (AEMIF)
–
EmbeddedICE-RT Logic for Real-Time
• Flash Memory Interfaces
Debug
–
NAND (8-/16-bit Wide Data)
• ARM9 Memory Architecture
–
OneNAND(16-bit Wide Data)
–
16K-Byte Instruction Cache
• Flash Card Interfaces
–
8K-Byte Data Cache
–
Two Multimedia Card (MMC) / Secure
–
32K-Byte RAM
Digital (SD/SDIO)
–
8K-Byte ROM
–
SmartMedia
–
Little Endian
• Enhanced Direct-Memory-Access (EDMA)
• MPEG4/JPEG Coprocessor
Controller (64 Independent Channels)
–
Fixed Function Coprocessor Supports:
• USB Port with Integrated 2.0 High-Speed PHY
• MPEG4 SP Codec at HD (720p), D1,
that Supports
VGA, SIF
–
USB 2.0 Full and High-Speed Device
• JPEG Codec up to 50M Pixels per
–
USB 2.0 Low, Full, and High-Speed Host
Second
• Three 64-Bit General-Purpose Timers (each
• Video Processing Subsystem
configurable as two 32-bit timers)
–
Front End Provides:
• One 64-Bit Watch Dog Timer
• Hardware IPIPE for Real-Time Image
• Three UARTs (One fast UART with RTS and
Processing
CTS Flow Control)
• CCD and CMOS Imager Interface
• Three Serial Port Interfaces (SPI) each with
• 14-Bit Parallel AFE (Analog Front End)
two Chip-Selects
Interface Up to 75 MHz
• One Master/Slave Inter-Integrated Circuit
• Glueless Interface to Common Video
(I2C) Bus™
Decoders
• Two Audio Serial Port (ASP)
• BT.601/BT.656 Digital YCbCr 4:2:2
–
I2S and TDM I2S
(8-/16-Bit) Interface
–
AC97 Audio Codec Interface
• Histogram Module
–
S/PDIF via Software
• Resize Engine
–
Standard Voice Codec Interface (AIC12)
–
Resize Images From 1/16x to 8x
–
SPI Protocol (Master Mode Only)
–
Separate Horizontal/Vertical Control
• Four Pulse Width Modulator (PWM) Outputs
–
Two Simultaneous Output Paths
• Four RTO (Real Time Out) Outputs
–
Back End Provides:
• Up to 104 General-Purpose I/O (GPIO) Pins
• Hardware On-Screen Display (OSD)
(Multiplexed with Other Device Functions)
• Composite NTSC/PAL video encoder
output
• On-Chip ARM ROM Bootloader (RBL) to Boot
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this document.
I2C-bus is a trademark of Texas Instruments.
Windows is a trademark of Microsoft.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright © 2007–2008, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.


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