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TMS320DM355 bảng dữ liệu(PDF) 73 Page - Texas Instruments |
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TMS320DM355 bảng dữ liệu(HTML) 73 Page - Texas Instruments |
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73 / 154 page  www.ti.com 3.6 PLL Controller (PLLC) 3.6.1 PLL Controller Module TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463D – SEPTEMBER 2007 – REVISED FEBRUARY 2008 This section describes the PLL Controllers for PLL1 and PLL2. See the TMS320DM35x Digital Media System-on-Chip (DMSoC) ARM Subsystem Reference Guide (literature number SPRUFB3) for more information on the PLL controllers. The DM355 has two PLL controllers that provide clocks to different components of the chip. PLL controller 1 (PLLC1) provides clocks to most of the components of the chip. PLL controller 2 (PLLC2) provides clocks to the DDR PHY. As a module, the PLL controller provides the following: • Glitch-free transitions (on changing PLL settings) • Domain clocks alignment • Clock gating • PLL bypass • PLL power down The various clock outputs given by the PLL controller are as follows: • Domain clocks: SYSCLKn • Bypass domain clock: SYSCLKBP • Auxiliary clock from reference clock: AUXCLK Various dividers that can be used are as follows: • Pre-PLL divider: PREDIV • Post-PLL divider: POSTDIV • SYSCLK divider: PLLDIV1, …, PLLDIVn • SYSCLKBP divider: BPDIV Multipliers supported are as follows: • PLL multiplier control: PLLM Submit Documentation Feedback Detailed Device Description 73 |
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