DIX4192IPFB datasheet(35/71 Pages) TI2

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DIX4192

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SBFS031F – FEBRUARY 2006 – REVISED SEPTEMBER 2016

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Figure 36. Register 0E: Receiver Control Register 2

7 (MSB)

0 (LSB)

LOL

RXAMLL

RXCKOD1

RXCKOD0

RXCKOE

Table 17. Register 0E: Receiver Control Register 2 Field Descriptions

RXCKOE

RXCKOE Output Enable

This bit is used to enable or disable the recovered clock output, RXCKO (pin 12). When disabled, the output is set to a high-impedance

state.

RXCKOE

RXCKO Output State

Disabled; the RXCKO output is set to high-impedance. (default)

Enabled; the recovered master clock is available at RXCKO.

RXCKOD[1:0]

RXCKO Output Clock Divider

These bits are used to set the clock divider at the output of PLL2. The output of the divider is the RXCKO clock, available internally or at

the RXCKO output (pin 12).

RXCKOD1

RXCKOD0

RXCKO Output Divider

Passthrough; no division is performed. (default)

Divide the PLL2 clock output by 2.

Divide the PLL2 clock output by 4.

Divide the PLL2 clock output by 8.

RXAMLL

Receiver Automatic Mute for Loss of Lock

This bit is used to set the automatic mute function for the DIR block when a loss of lock is indicated by both the AES3 decoder and PLL2.

RXAMLL

Receiver Auto-Mute Function

Disabled (default)

Enabled; audio data output from the DIR block is forced low for a loss of lock condition.

LOL

Receiver Loss of Lock Mode for the Recovered Clock (output from PLL2)

This bit is used to set the mode of operation for PLL2 when a loss of lock condition occurs.

LOL

Receiver PLL2 Operation

The PLL2 output clock is stopped for a loss of lock condition. (default)

The PLL2 output clock free runs when a loss of lock condition occurs.

Figure 37. Register 0F: Receiver PLL1 Configuration Register 1

7 (MSB)

0 (LSB)

Figure 38. Register 10: Receiver PLL1 Configuration Register 2

7 (MSB)

0 (LSB)

D13

D12

D11

D10

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