DIX4192IPFB datasheet(33/71 Pages) TI2

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DIX4192

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SBFS031F – FEBRUARY 2006 – REVISED SEPTEMBER 2016

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Table 11. Register 08: Transmitter Control Register 2 Field Descriptions (continued)

BYPMUX[1:0]

Bypass Multiplexer Source Selection

These bits select the line receiver output to be used as the bypass multiplexer data source.

BYPMUX1

BYPMUX0

Line Receiver Output Selection

RX1 (default)

RX2

RX3

RX4

Figure 31. Register 09: Transmitter Control Register 3

7 (MSB)

0 (LSB)

VALSEL

TXCUS1

TXCUS0

Table 12. Register 09: Transmitter Control Register 3 Field Descriptions

TXCUS[1:0]

Transmitter Channel Status and User Data Source

These bits select the source of the channel status (or C) data and user (or U) data which is used to load the DIT User Access (UA) buffers.

TXCUS1

TXCUS0

DIT UA Buffer Source

The buffers will not be updated. (default)

The buffers are updated through the SPI or I2C host interface.

The buffers are updated through the DIR RA buffers.

The first 10 bytes of the buffers are updated through the SPI or I2C host, while the

remainder of the buffers are updated through the DIR RA buffers.

VALSEL

Transmitter Validity Bit Source

This bit is used to select the source for the validity (or V) bit in the AES3-encoded output data stream.

VALSEL

Validity (or V) Bit Source Selection

The VALID bit in control register 0x07.

The V bit is transferred from the DIR block with zero latency.

Figure 32. Register 0A: DIT Status (Read-Only)

7 (MSB)

0 (LSB)

TSLIP

TBTI

Table 13. Register 0A: DIT Status (Read-Only) Field Descriptions

TBTI

Transmitter Buffer Transfer Status, Active High

When DIT User Access (UA) to Transmitter Access (TA) buffer transfers are enabled (the TXBTD bit in control register 0x08 is set to

0), and the TBTI interrupt is unmasked (the MTBTI bit in control register 0x0B is set to 1), the TBTI bit will be set to 1 when the UA-to-

TA buffer transfer has completed. This configuration also causes the INT output (pin 23) to be driven low and the TX bit in status

TSLIP

Transmitter Source Data Slip Status, Active High

The TSLIP bit will be set to 1 when either an asynchronous data slip or block start condition is detected, and the TSLIP interrupt is

unmasked (the MTSLIP bit in control register 0x0B is set to 1). The BSSL bit in control register 0x07 is used to set the source for this

interrupt.

The TSLIP bit being forced to 1 will also cause the INT output (pin 23) to be driven low and the TX bit in status register 0x02 to be set

to 1, indicating that an interrupt has occurred.

Figure 33. Register 0B: DIT Interrupt Mask Register

7 (MSB)

0 (LSB)

MTSLIP

MTBTI

Table 14. Register 0B: DIT Interrupt Mask Register Field Descriptions

MBTI

Transmitter Buffer Transfer Interrupt Mask

MTBI

BTI Interrupt Mask

BTI interrupt is masked. (default)

BTI interrupt is enabled.

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