DIX4192IPFB datasheet(19/71 Pages) TI2

19 / 71 page

PL 1

AE 3

Decoder

Pulse

Generator

PL 2

128f

256f

512f

Clock

Divider

Divide by

1,2, 4,or8

DataStream

De-M x

RX1+(pin1)

RX1 (pin2)

RX2+(pin3)

RX2 (pin4)

RX3+(pin5)

RX3 (pin6)

RX4+(pin7)

RX4 (pin8)

LOCK

(pin 11)

RXCKO

(pin 12)

RXCKO

BYPMUX[10

: ]

R MUX[

1:0]

RXCLK

MC K

RXCKI

RXCKOF[1:0]

Ch1

(Left)

Audio

Ch2

(Right)

Audio

Cha ne

Status

Channel

Status

User

Daa

User

Daa

UserAccess

(UA)Buffers

Receiver

Access

(RA)Buffers

DIT

ToSPI orI CHostInterface

Receiver

Sy c

Generator

RCV_SYNC

Errorand

StatusOutputs

ToDIT Buffer

andLine Driver

Reference

Clock

Source

DIT

SY C

BLS

(input)

BLS

(output)

Block Start

(Frame 0startshere)

DIX4192

www.ti.com

SBFS031F – FEBRUARY 2006 – REVISED SEPTEMBER 2016

Product Folder Links: DIX4192

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Feature Description (continued)

Figure 12. DIT Block Start Timing

9.3.6 Digital Interface Receiver (DIR) Operation

The DIR performs AES3 decoding and clock recovery and provides the differential line receiver functions. The

lock range of the DIR includes frame and sampling rates from 20 kHz to 216 kHz. Figure 13 shows the functional

block diagram for the DIR.

Four differential line receivers are used for signal conditioning the encoded input data streams. The receivers can

be externally configured for either balanced or unbalanced cable interfaces, as well as interfacing with CMOS

logic level inputs from optical receivers or external logic circuitry. See Figure 14 for a simplified schematic for the

line receiver. External connections are discussed in Receiver Input Interfacing.

Figure 13. Digital Interface Receiver (DIR) Functional Block Diagram

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