STM32L412C8I6TR datasheet(131/192 Pages) STMICROELECTRONICS

tên linh kiện	STM32L412C8I6TR

Giải thích chi tiết về linh kiện	Ultra-low-power Arm® Cortex®-M4 32-bit MCUFPU, 100DMIPS, up to 128KB Flash, 40KB SRAM, analog, ext. SMPS

PDF	192 Pages

Scroll/Zoom	100%

nhà sản xuất	STMICROELECTRONICS [STMicroelectronics]

Trang chủ	http://www.st.com

Logo

131 / 192 page

DS12469 Rev 4

131/192

STM32L412xx

Electrical characteristics

163

All I/Os are CMOS- and TTL-compliant (no software configuration required). Their

characteristics cover more than the strict CMOS-technology or TTL parameters. The

coverage of these requirements is shown in Figure 26 for standard I/Os, and in Figure 26 for

5 V tolerant I/Os.

Figure 26. I/O input characteristics

Output driving current

The GPIOs (general purpose input/outputs) can sink or source up to ±8 mA, and sink or

source up to ± 20 mA (with a relaxed VOL/VOH).

1. Refer to Figure 26: I/O input characteristics.

2. Tested in production.

3. Guaranteed by design.

4. This value represents the pad leakage of the IO itself. The total product pad leakage is provided by this formula:

ITotal_Ileak_max = 10 µA + [number of IOs where VIN is applied on the pad] ₓ Ilkg(Max).

5. All FT_xx GPIOs except FT_u and PC3 I/O.

6. Max(VDDXXX) is the maximum value of all the I/O supplies. Refer to Table: Legend/Abbreviations used in the pinout table.

7. To sustain a voltage higher than Min(VDD, VDDA, VDDUSB) +0.3 V, the internal Pull-up and Pull-Down resistors must be

disabled.

8. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This

PMOS/NMOS contribution to the series resistance is minimal (~10% order).

STM32L412C8I6TR bảng dữ liệu(PDF) 131 Page - STMicroelectronics