STM32L412C8I6TR datasheet(47/192 Pages) STMICROELECTRONICS

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DS12469 Rev 4

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STM32L412xx

Functional overview

3.25

Serial peripheral interface (SPI)

Three SPI interfaces allow communication up to 40 Mbits/s in master and up to 24 Mbits/s

slave modes, in half-duplex, full-duplex and simplex modes. The 3-bit prescaler gives 8

master mode frequencies and the frame size is configurable from 4 bits to 16 bits. The SPI

interfaces support NSS pulse mode, TI mode and Hardware CRC calculation.

All SPI interfaces can be served by the DMA controller.

3.26

Universal serial bus (USB)

The STM32L412xx devices embed a full-speed USB device peripheral compliant with the

USB specification version 2.0. The internal USB PHY supports USB FS signaling,

embedded DP pull-up and also battery charging detection according to Battery Charging

Specification Revision 1.2. The USB interface implements a full-speed (12 Mbit/s) function

interface with added support for USB 2.0 Link Power Management. It has software-

configurable endpoint setting with packet memory up-to 1 KB and suspend/resume support.

It requires a precise 48 MHz clock which can be generated from the internal main PLL (the

clock source must use a HSE crystal oscillator) or by the internal 48 MHz oscillator in

automatic trimming mode. The synchronization for this oscillator can be taken from the USB

data stream itself (SOF signalization) which allows crystal less operation.

3.27

Clock recovery system (CRS)

The STM32L412xx devices embed a special block which allows automatic trimming of the

internal 48 MHz oscillator to guarantee its optimal accuracy over the whole device

operational range. This automatic trimming is based on the external synchronization signal,

which could be either derived from LSE oscillator, from an external signal on CRS_SYNC

pin or generated by user software. For faster lock-in during startup it is also possible to

combine automatic trimming with manual trimming action.

3.28

Quad SPI memory interface (QUADSPI)

The Quad SPI is a specialized communication interface targeting single, dual or quad SPI

flash memories. It can operate in any of the three following modes:

•

Indirect mode: all the operations are performed using the QUADSPI registers

•

Status polling mode: the external flash status register is periodically read and an

interrupt can be generated in case of flag setting

•

Memory-mapped mode: the external Flash is memory mapped and is seen by the

system as if it were an internal memory

Both throughput and capacity can be increased two-fold using dual-flash mode, where two

Quad SPI flash memories are accessed simultaneously.

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