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PCM1738E/2K.B bảng dữ liệu(PDF) 36 Page - Texas Instruments

tên linh kiện PCM1738E/2K.B
Giải thích chi tiết về linh kiện  24-Bit, 192-kHz Sampling, Advanced Segment, Audio-Stereo Digital-to-Analog Converter
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PCM1738E/2K.B bảng dữ liệu(HTML) 36 Page - Texas Instruments

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APPLICATION FOR DSD FORMAT (DSD MODE) INTERFACE
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15
AlwaysSetLOW
DATA-L
AlwaysSetLOW
BitClock(n
f )
´ S
DATA-R
DSDDecoder
Mode
Control
RST
ZEROL
ZEROR
N/A (LRCK)
DATAL (DATA)
N/A (BCK)
BCK(SCKI)
DGND
V
DD
SCKO
MDO
MDI
MC
CS
V
3
CC
AGND2
I
OUTL–
I
OUTL+
V
CC2
V
CC1
V
COM3
I
REF
V
COM2
V
COM1
AGND1
I
OUTR+
I
OUTR–
DATAR(MUTE)
Analog
OutputStage
SameasStandard
Application
B0202-01
():OriginalPinName
FEATURES
PIN ASSIGNMENT WHEN IN DSD-FORMAT INTERFACE
PCM1738
SBAS174C – FEBRUARY 2002 – REVISED FEBRUARY 2007
Figure 44. Connection Diagram for DSD Format Interface
This mode is used for interfacing directly to a DSD decoder, found in Super Audio CD (SACD) applications.
DSD mode provides a low-pass filtering function to convert the 1-bit oversampled data stream to the analog
domain. The filtering is provided using an analog FIR filter structure. Four FIR responses are available and may
be selected via the serial control interface. Refer to the Typical Performance Curves section of this data sheet
for analog FIR plots. See Figure 45 and Figure 46 for timing and interface specification in DSD mode.
Several pins are redefined for DSD-mode operation. These include:
• DATA (pin 5)—DATAL, L-channel DSD data input
• MUTE (pin 15)—DATAR, R-channel DSD data input
• SCKI (pin 7)—bit clock (BCK) for DSD data
• LRCK (pin 4)—set LOW
• BCK (pin 6)—set LOW
Typical connection to a DSD decoder is shown in Figure 44.
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