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PCM1738E/2K.B bảng dữ liệu(PDF) 34 Page - Texas Instruments

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PCM1738E/2K.B bảng dữ liệu(HTML) 34 Page - Texas Instruments

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t
(BCH)
t
(BCL)
t
(LB)
t
(BCY)
WDCK
BCK
DATAL
DATAR
t
(DS)
1.4V
1.4V
1.4V
T0199-01
t
(DH)
t
(BL)
PCM1738
SBAS174C – FEBRUARY 2002 – REVISED FEBRUARY 2007
PARAMETER
MIN
MAX
UNIT
t(BCY)
BCK clock cycle time
18
ns
tw(BCL)
BCK pulse duration, LOW
7
ns
tw(BCH)
BCK pulse duration, HIGH
7
ns
t(BL)
BCK rising edge to WDCK falling edge
5
ns
t(LB)
WDCK falling edge to BCK rising edge
5
ns
t(DS)
DATA setup time
5
ns
t(DH)
DATA hold time
5
ns
Figure 43. Audio Interface Timing for External Digital Filter (Internal DF Bypass Mode) Application
Table 5. Register Mapping in the External Digital-Filter Mode
REGISTER
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
16
W/R
0
0
1
0
0
0
0
–(1)
–
–
–
–
–
–
–
17
W/R
0
0
1
0
0
0
1
–
–
–
–
–
–
–
–
18
W/R
0
0
1
0
0
1
0
–
FMT2
FMT1
FMT0
–
–
DME(2)
–
19
W/R
0
0
1
0
0
1
1
–
–
–
OPE
CLKD
CLKE
–
INZD
20
W/R
0
0
1
0
1
0
0
RSV
SRST
MRST
DFTH(2)
RSV
RSV
OS1
OS0
21
R
0
0
1
0
1
0
1
RSV
RSV
RSV
RSV
RSV
RSV
ZFGR
ZFGL
(1)
– = function disabled. No operation regardless of data setting.
(2)
These bits are required for selection of the external digital-filter mode.
FMT[2:0] Audio Data Format Selection
These bits are available for read/write.
Default Value: 000
FMT[2:0]
Audio Data Format Select
000
16-bit, right-justified format (default)
001
20-bit, right-justified format
010
24-bit, right-justified format
Other
Reserved
34
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