DSP56721 datasheet(18/54 Pages) FREESCALE

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SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1

Freescale Semiconductor

2.2.1

Serial Host Interface (SHI) SPI Protocol Timing

See Table 11 for SHI SPI protocol timing parameters and Figure 15, Figure 16, Figure 17, and Figure 18 for timing diagrams.

Table 11. Serial Host Interface SPI Protocol Timing Parameters

No.

Characteristics1,3,4

Mode

Filter Mode

Expression

Min

Max

Unit

Minimum serial clock cycle = tSPICC(min)

Master/Slave

Bypassed

10 x TC + 9

59.0

–

Very Narrow

10 x TC + 9

59.0

–

Narrow

10 x TC + 133

183.0

–

Wide

10 x TC + 333

373.0

–

Tolerable Spike width on data or clock in

–

Bypassed

–

Very Narrow

–

Narrow

–

Wide

–

100

Serial clock high period

Master

Bypassed

0.5 x (tSPICC -10)

33.0

–

Very Narrow

0.5 x (tSPICC -10)

33.0

–

Narrow

0.5 x (tSPICC -10)

86.0

–

Wide

0.5 x (tSPICC -10)

121.5

–

Slave

Bypassed

2.5 x TC + 12

22.5

–

Very Narrow

2.5 x TC + 12

22.5

–

Narrow

2.5 x TC + 102

114.5

–

Wide

2.5 x TC + 189

201.5

–

Serial clock low period

Master

Bypassed

0.5 x (tSPICC -10)

33.0

–

Very Narrow

0.5 x (tSPICC -10)

33.0

–

Narrow

0.5 x (tSPICC -10)

86.0

–

Wide

0.5 x (tSPICC -10)

121.5

–

Slave

Bypassed

2.5 x TC + 12

22.5

–

Very Narrow

2.5 x TC + 12

22.5

–

Narrow

2.5 x TC + 102

114.5

–

Wide

2.5 x TC + 189

201.5

–

Serial clock rise/fall time

Master

Slave

–

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