DSP56721 datasheet(24/54 Pages) FREESCALE

tên linh kiện	DSP56721

Giải thích chi tiết về linh kiện	SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors

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SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1

Freescale Semiconductor

Figure 18. SPI Slave Timing Diagram (CPHA = 1)

2.2.2

Serial Host Interface (SHI) I2C Protocol Timing

See Table 12 for SHI I2C protocol timing parameters and Figure 19 for the timing diagram.

Table 12. SHI I2C Protocol Timing Parameters

Standard I2C

No.

Characteristics1,2,3,4,5

Symbol/

Expression

Standard

Fast-Mode

Unit

Min

Max

Min

Max

Tolerable Spike Width on SCL or SDA

Filters Bypassed

Very Narrow Filters enabled

Narrow Filters enabled

Wide Filters enabled.

–

100

–

100

SCL clock frequency

FSCL

–

100

–

400

kHz

SCL clock cycle

TSCL

–

2.5

–

μs

Bus free time

TBUF

4.7

–

1.3

–

μs

Start condition set-up time

TSUSTA

4.7

–

0.6

–

μs

(Input)

SCK (CPOL = 0)

(Input)

SCK (CPOL = 1)

(Input)

MISO

(Output)

MOSI

(Input)

HREQ

(Output)

MSB

LSB

MSB

Valid

LSB

Valid

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