DSP56721 datasheet(26/54 Pages) FREESCALE

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SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1

Freescale Semiconductor

2.2.3

Programming the SHI I2C Serial Clock

The programmed serial clock cycle, TI2CCP, is specified by the value of the HDM[7:0] and HRS bits of the HCKR (SHI clock

control register).

The expression for TI2CCP is

TI2CCP = [TC × 2 × (HDM[7:0] + 1) × (7 × (1 – HRS) + 1)]

Eqn. 1

where

— HRS is the pre scaler rate select bit. When HRS is cleared, the fixed

divide-by-eight pre scaler is operational. When HRS is set, the pre scaler is bypassed.

— HDM[7:0] are the divider modulus select bits. A divide ratio from 1 to 256 (HDM[7:0] = $00 to $FF) may be

selected.

In I2C mode, the user may select a value for the programmed serial clock cycle from

× T

(if HDM[7:0] = $02 and HRS = 1)

Eqn. 2

4096

× T

C (if HDM[7:0] = $FF and HRS = 0)

Eqn. 3

The programmed serial clock cycle (TI2CCP) should be chosen in order to achieve the desired SCL serial clock cycle (TSCL), as

shown in Equation 4.

TI2CCP + 3 × TC + 45ns + TR

(Nominal, SCL Serial Clock Cycle (TSCL) generated as master)

Eqn. 4

Figure 19. I2C Timing Diagram

SCL

SDA

HREQ

Stop

Start

MSB

LSB

ACK

Stop

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