DSP56721 datasheet(15/54 Pages) FREESCALE

15 / 54 page

SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1

Freescale Semiconductor

Duration of level sensitive IRQA assertion to ensure interrupt service

(when exiting Stop)1, 2, 3

• PLL is active during Stop and Stop delay is enabled (OMR Bit 6 = 0)

(128K × T

655

–

μs

• PLL is active during Stop and Stop delay is not enabled (OMR Bit 6 =

× T

125

–

• PLL is not active during Stop and Stop delay is enabled (OMR Bit 6 =

(128K x TC) +

TLOCK

855

–

μs

• PLL is not active during Stop and Stop delay is not enabled (OMR Bit

6 = 1)

(25 x TC) + TLOCK

200

–

μs

• Delay from IRQA, IRQB, IRQC, IRQD, NMI assertion to

general-purpose transfer output valid caused by first interrupt

instruction execution1

10 x TC + 3.8

–

53.8

Interrupt Requests Rate1

• ESAI, ESAI_1, ESAI_2, ESAI_3, SHI, SHI_1, Timer, Timer_1

12 x TC

–60.0

• DMA

8 x TC

–40.0

•IRQ, NMI (edge trigger)

8 x TC

–40.0

•IRQ (level trigger)

12 x TC

–60.0

DMA Requests Rate

• Data read from ESAI, ESAI_1, ESAI_2, ESAI_3, SHI, SHI_1

6 x TC

–30.0

• Data write to ESAI, ESAI_1, ESAI_2, ESAI_3, SHI, SHI_1

7 x TC

–35.0

• Timer, Timer_1

2 x TC

–10.0

•IRQ, NMI (edge trigger)

3 x TC

–15.0

Notes:

When using fast interrupts and when IRQA, IRQB, IRQC, and IRQD are defined as level-sensitive, timings 19 through 21 apply to

prevent multiple interrupt service. To avoid these timing restrictions, the Edge-triggered mode is recommended when using fast

interrupts. Long interrupts are recommended when using Level-sensitive mode.

For PLL disable, if using an external clock (PCTL Bit 13 = 1), no stabilization delay is required and recovery time will be defined by

the OMR Bit 6 settings.

For PLL enable, (if bit 12 of the PCTL register is 0), the PLL is shut down during Stop. Recovering from Stop requires the PLL to get

locked. The PLL lock procedure duration, PLL Lock Cycles (PLC), may be in the range of 200

μs.

Periodically sampled and not 100% tested.

RESET duration is measured during the time in which RESET is asserted, VDD is valid, and the EXTAL input is active and valid. When

VDD is valid, but the other “required RESET duration” conditions (as specified above) have not been yet met, the device circuitry will

be in an uninitialized state that can result in significant power consumption and heat-up. Designs should minimize this state to the

shortest possible duration.

Table 9. Reset, Stop, Mode Select, and Interrupt Timing Parameters

No.

Characteristics

Expression

Min

Max

Unit

DSP56721 bảng dữ liệu(PDF) 15 Page - Freescale Semiconductor, Inc

DSP56721 bảng dữ liệu(HTML) 15 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54

bảng dữ liệu tải về

Link URL