DSP56720 datasheet(35/54 Pages) FREESCALE

35 / 54 page

SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1

Freescale Semiconductor

Figure 28. Test Access Port Timing Diagram

2.2.8

Watchdog Timer Timing

For watchdog timer timing, see Table 17.

2.2.9

Host Data Interface (HDI24) Timing

The HDI24 module is only on the DSP56721 device; the DSP56720 device does not have a HDI24 module. Also, only 16 bits

of the HDI24 interface are pinned out on the DSP56721 device. See Table 18 for HDI24 timing and Figure 29, Figure 30,

Figure 30, Figure 31, Figure 32, Figure 33, Figure 34, and Figure 35 for timing diagrams.

Table 17. Watchdog Timer Timing Parameters

No.

Characteristics

Expression

Min

Max

Unit

120

Delay from time-out to fall of WDT, WDT_1

× T

10.0

–

121

Delay from timer clear to rise of WDT, WDT_1

× Tc

10.0

–

Table 18. HDI24 Timing Parameters

No.

Characteristics

Expression

200 MHz

Unit

Min

Max

317

Read data strobe assertion width

HACK read assertion width

TC + 9.9

14.9

–

318

Read data strobe deassertion width

HACK read deassertion width

–9.9

–

319

Read data strobe deassertion width

after “Last Data Register” reads

4,5

or between two consecutive CVR, ICR, or ISR reads

HACK deassertion width after “Last Data Register” reads

4,5

× T

C + 6.6

16.6

–

VIH

VIL

116

117

118

119

118

TCK

(Input)

TDI

TMS

(Input)

TDO

(Output)

TDO

(Output)

TDO

(Output)

Input Data Valid

Output Data Valid

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