FS32K112BFT0M datasheet(11/85 Pages) NXP

11 / 85 page

1. Typical conditions assumes VDD = VDDA = VREFH = 5 V, temperature = 25 °C and typical silicon process unless otherwise

stated.

2. As VDD varies between the minimum value and the absolute maximum value the analog characteristics of the I/O and the

ADC will both change. See section I/O parameters and ADC electrical specifications respectively for details.

3. S32K148 will operate from 2.7 V when executing from internal FIRC. When the PLL is engaged S32K148 is guaranteed to

operate from 2.97 V. All other S32K family devices operate from 2.7 V in all modes.

4. VDD and VDDA must be shorted to a common source on PCB. The differential voltage between VDD and VDDA is for RF-AC

only. Appropriate decoupling capacitors to be used to filter noise on the supplies. See application note AN5032 for

reference supply design for SAR ADC.

5. VREFH should always be equal to or less than VDDA + 0.1 V and VDD + 0.1 V

6. Open drain outputs must be pulled to VDD.

7. When input pad voltage levels are close to VDD or VSS, practically no current injection is possible.

4.3 Thermal operating characteristics

Table 3. Thermal operating characteristics

Symbol

Parameter

Value

Unit

Min.

Typ.

Max.

TA C-Grade Part

Ambient temperature under bias

−40

—

851

℃

TJ C-Grade Part

Junction temperature under bias

−40

—

1051

℃

TA V-Grade Part

Ambient temperature under bias

−40

—

1051

℃

TJ V-Grade Part

Junction temperature under bias

−40

—

1251

℃

TA M-Grade Part

Ambient temperature under bias

−40

—

1252

℃

TJ M-Grade Part

Junction temperature under bias

−40

—

1352

℃

1. Values mentioned are measured at ≤ 112 MHz in HSRUN mode.

2. Values mentioned are measured at ≤ 80 MHz in RUN mode.

General

S32K1xx Data Sheet, Rev. 11, 06/2019

NXP Semiconductors

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