FS32K112BFT0M datasheet(44/85 Pages) NXP

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Table 27. 12-bit ADC operating conditions (continued)

Symbol Description

Conditions

Min.

Typ.1

Max.

Unit

Notes

fADCK

ADC conversion clock

frequency

Normal usage

MHz

3, 4

fCONV

ADC conversion frequency

No ADC hardware

averaging.5 Continuous

conversions enabled,

subsequent conversion

time

46.4

928

1160

Ksps

6, 7

ADC hardware averaging

set to 32. 5 Continuous

conversions enabled,

subsequent conversion

time

1.45

36.25

Ksps

6, 7

1. Typical values assume VDDA = 5 V, Temp = 25 °C, fADCK = 40 MHz, RAS=20 Ω, and CAS=10 nF unless otherwise stated.

Typical values are for reference only, and are not tested in production.

2. For packages without dedicated VREFH and VREFL pins, VREFH is internally tied to VDDA, and VREFL is internally tied to VSS.

To get maximum performance, reference supply quality should be better than SAR ADC. See application note AN5032 for

details.

3. Clock and compare cycle need to be set according to the guidelines mentioned in the Reference Manual .

4. ADC conversion will become less reliable above maximum frequency.

5. When using ADC hardware averaging, see the Reference Manual to determine the most appropriate setting for AVGS.

6. Numbers based on the minimum sampling time of 275 ns.

7. For guidelines and examples of conversion rate calculation, see the Reference Manual section 'Calibration function'

Figure 13. ADC input impedance equivalency diagram

ADC electrical specifications

S32K1xx Data Sheet, Rev. 11, 06/2019

NXP Semiconductors

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