ADF4382ABCCZ datasheet(11/82 Pages) AD

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Data Sheet

ADF4382A

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

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Rev. A | 11 of 82

Figure 6. Pin Configuration

Table 6. Pin Function Descriptions

Pin No.

Mnemonic

Description

1, 2, 4, 10, 12, 14, 16, 18, 19,

21, 23, 25, 26, 41, 48

GND

Negative Power Supply (Ground). Tie the GND pins directly to the ground pad.

V3_NDIV

3.15 V to 3.45 V Positive Power Supply Pin for the PLL Feedback Divider Circuitry. Short the V3_NDIV pin to the

other pins in the 3.3 V Power Supply Group 1.

V3_VCOB

3.15 V to 3.45 V Positive Power Supply Pin for the Bias Circuitry and Digital Logic Control Portion of the VCO.

Short the V3_VCOB pin to the other pins in the 3.3 V Power Supply Group 2.

VG_BIAS

Bias Decoupling Pin. Connect uninstalled 0402, 0.1 μF capacitor footprint to GND.

VTUNE

VCO Tuning Input. This frequency control pin is normally connected to the external loop filter.

V5_CAL

4.75 V to 5.25 V Positive Power Supply Pin for VCO Calibration Circuitry. The V5_CAL pin can be shorted to the

V5_VCO supply plane.

V5_VCO

4.75 V to 5.25 V Positive Power Supply Pin for the VCO Circuitry.

V3_OUTDIV

3.15 V to 3.45 V Positive Power Supply Pin for the Output Divider Circuitry. Short the V3_OUTDIV pin to the other

pins in the 3.3 V Power Supply Group 2.

V3_RFOUT2

3.15 V to 3.45 V Positive Power Supply Pin for the RFOUT 2 Buffer Circuitry. Short the V3_RFOUT2 pin to the

other pins in the 3.3 V Power Supply Group 2.

15, 17

RFOUT2N, RFOUT2P

RF Output 2 Output Signal. The VCO output divider is buffered and presented differentially on the RFOUT2N and

RFOUT2P pins. The outputs have a 50 Ω (typical) output resistance per side (100 Ω differential). The far end

of the transmission line is typically terminated with 100 Ω connected across the outputs. The output amplitude is

programmable via the serial port.

20, 22

RFOUT1N, RFOUT1P

RF Output 1 Output Signal. The VCO output divider is buffered and presented differentially on the RFOUT1N and

REFOUT1P pins. The outputs have 50 Ω (typical) output resistance per side (100 Ω differential). The far end of

the transmission line is typically terminated with 100 Ω connected across the outputs. The output amplitude is

programmable via the serial port.

V3_RFOUT1

3.15 V to 3.45 V Positive Power Supply Pin for the RFOUT 1 Buffer Circuitry. Short the V3_RFOUT1 pin to the

other pins in the 3.3 V Power Supply Group 2.

LKDET

PLL Lock Detect. This output presents the lock status of the PLL. The PLL is locked when LKDET is a logic high.

DELADJ

Delay Adjust Input Signal. Logic 0 ensures that the delay of the RF output signal is reduced after DELSTR is

asserted. Logic 1 ensures that the delay of the RF output signal is increased after DELSTR is asserted.

DELSTR

Delay Strobe Input Signal. A rising edge on this signal indicates that an adjustment is needed. The adjustment is

then made on the falling edge.

V3_LS

3.15 V to 3.45 V Positive Power Supply Pin for the Internal Level Shift Circuitry. Short the V3_LS pin to the other

pins in the 3.3 V Power Supply Group 1.

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