ADF4382ABCCZ datasheet(32/82 Pages) AD

32 / 82 page

Data Sheet

ADF4382A

APPLICATIONS INFORMATION

analog.com

Rev. A | 32 of 82

POWER-UP AND INITIALIZATION SEQUENCE

The following steps describe the recommended power-up and initi-

alization sequence of the ADF4382A:

1. Apply specified voltages to the V5V, V3.3V_1, and V3.3V_2 power

supply groups. The ADF4382A is in full power-down mode at

this point and SPI programming is not possible.

2. Set the CE pin to a logic high. It is acceptable to connect the

CE pin to the V3_LDO pin via a pull-up resistor. Therefore, Step

1 and Step 2 are performed coincidentally.

3. After waiting ≥200 μs for all SPI register bits to settle to their

power-on reset (POR) state, begin programming the SPI to

configure the ADF4382A to a desired state. The following is the

recommended SPI programming sequence:

a. Set the SDO_ACTIVE and CMOS_OV bits to a desired

state for future readback operations.

b. Program all required register addresses. The ordering of

programming does not matter except to ensure that register

0x010 is the last register write. There are several required

reserved register field settings provided in Register Map

that are required for proper device operation.

4. The ADF4382A remains in power-down mode until the PD_ALL

bit is programmed to 0. After PD_ALL is disabled, VTUNE is

precharged in the loop filter to reduce VCO calibration time.

The precharge time required before starting a VCO calibration

depends on the largest value of capacitor in the loop filter. The

wait time is:

750 × CMAX,whereCMAXisthemaximumvalue

capacitor in the loop filter. The minimum precharge time is 50

μs.

5. A write to Register 0x010 starts a VCO autocalibration. At this

point, the ADF4382A is fully operational and new frequencies

can be programmed as often as desired. The following steps

are information for the PD_ALL bit and the CE pin.

6. Setting PD_ALL to 1 power down the ADF4382A, retaining

the latest programmed SPI settings and full SPI programming

capability.

7. If only the state of PD_ALL was modified in Step 6, setting

PD_ALL to 0 returns the ADF4382A to the frequency program-

med in Step 5. After a 10 μs wait, all circuit blocks are

completely powered up internally. This 10 μs wait does not

include the frequency settling time associated with the loop filter

bandwidth.

8. Toggling the CE pin level causes the ADF4382A to return to

full power-down mode and return the SPI registers to the POR

state (see Step 2 and Step 3).

Figure 59. Power-Up and Initialization

Programming Procedure

There are two different methods to power up the ADF4382A. The

most commonly used method is provided in the Standard Power-Up

and Initialization Sequence, Automatic VCO Calibration section is

mandatory at the initial device power-up.

The method provided in the Fast Power-Up and Initialization, Man-

ually Programmed VCO Calibration Settings section is an optional

power-up procedure after the initial power-up.

ADF4382ABCCZ bảng dữ liệu(PDF) 32 Page - Analog Devices

ADF4382ABCCZ bảng dữ liệu(HTML) 32 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82

bảng dữ liệu tải về

Link URL