ADF4382ABCCZ datasheet(5/82 Pages) AD

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Data Sheet

ADF4382A

SPECIFICATIONS

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Rev. A | 5 of 82

Parameter

Symbol

Min

Typ

Max

Unit

Test Conditions/Comments

VCO

Fundamental Frequency Range

fVCO

11.5

GHz

VCO Autocalibration Time

100

µs

Tuning Sensitivity

KVCO

50 to 150

MHz/V

KVCO2,3

Divided Reference Clock (DIV_RCLK) VCO

Calibration Frequency

fDIV_RCLK

125

MHz

Must set DCLK_MODE = 1, when fDIV_RCLK >

80 MHz

FEEDBACK (N) AND OUTPUT DIVIDER (O)

4095

Integer mode

4095

Fractional mode

1, 2, and 4

CLOCK OUTPUTS (RFOUT1P and RFOUT1N,

RFOUT2P and RFOUT2N)

Differential termination = 100 Ω for all

RF output (RFOUT) specifications unless

otherwise noted

Output Frequency

fOUT

11.5

GHz

Divide by 2

5.75

10.5

GHz

Divide by 4

2.875

5.25

GHz

Differential RF Output Power

PRFOUT

dBm

RFOUT1_OPWR = RFOUT2_OPWR = 11,

fOUT = 11.5 GHz

dBm

RFOUT1_OPWR = RFOUT2_OPWR = 11,

fOUT =14 GHz

dBm

RFOUT1_OPWR = RFOUT2_OPWR = 11,

fOUT = 20 GHz

Output Resistance

100

Differential

Output Common Mode

3.3 − VOD4

Output Rise Time

20% to 80%, RFOUT1_OPWR =

RFOUT2_OPWR = 1

Output Fall Time

80% to 20%, RFOUT1_OPWR =

RFOUT2_OPWR = 1

Output Duty Cycle

Skew, RFOUT1 to RFOUT2

±3

REFERENCE INPUT TO OUTPUT DELAY

Device setup for all delay specifications

unless noted as follows, measure rising

reference edge at reference input to rising

edge at RFOUT output

Propagation Delay

tPD

190

REF_SEL = 0 and REF_SEL = 1

Propagation Delay Temperature Coefficient

tPD-TC

0.06

ps/°C

REF_SEL = 0

LOGIC INPUTS (CSB, SCLK, SDIO, DELADJ and

DELSTR)

Input High Voltage

VINH

1.2

Input Low Voltage

VINL

0.6

Input Current

IIH/IIL

±1

µA

Input Capacitance

CIN

LOGIC INPUT (CE)

Input High Voltage

VINH-3V

1.8

Input Low Voltage

VINL-3V

0.8

Input Current

IIH-3V/IIL-3V

±1

μA

Input Capacitance

CIN-3V

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