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AX88796BLF bảng dữ liệu(PDF) 77 Page - ASIX Electronics Corporation

tên linh kiện AX88796BLF
Giải thích chi tiết về linh kiện  Low-pin-count Non-PCI 8/16-bit 10/100M Fast Ethernet Controller
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nhà sản xuất  ASIX [ASIX Electronics Corporation]
Trang chủ  http://www.asix.com.tw
Logo ASIX - ASIX Electronics Corporation

AX88796BLF bảng dữ liệu(HTML) 77 Page - ASIX Electronics Corporation

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ASIX ELECTRONICS CORPORATION
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AX88796BLF / AX88796BLI
Appendix A4: co-work with 32-bit processor
An example, AX88796B co-work with Samsung 2440 processor. (32-bit processor with external 16-bit bus)
AX88796B’s bus setting as ISA mode. (Without external resister connect to EECS and EECK) Host can use burst
read mode, it is useful host processor increment its address when moving AX88796B received data.
AX88796B supports two kinds of Data Port for receiving/transmitting packets from/to AX88796B. One is the PIO
Data Port (offset 10h); the other one is the SRAM-like Data Port (e.g. offset 800h ~ FFFh for Samsung2440
processor as described in below figure). The SRAM-like Data Port address range depends on which address line of
host processor is being connected to the address line SA5/FIFO_SEL of AX88796B.
Software on host CPU can issue Single Data Read/Write command to both PIO Data Port and SRAM-like Data Port.
However, to use Burst Data Read/Write commands, one has to use SRAM-like Data Port, which requires
SA5/FIFO_SEL (pin 45) of AX88796B connecting to an upper address line of host CPU. AX88796B with Samsung
2440 processor reference schematic has SA5/FIFO_SEL pin connected to upper address line (i.e. A11 of Samsung
2440) for supporting Burst Data Read/Write commands.
Read
Write
Host Addr
A[11:0]
SD[15:8]
SD[7:0]
AX88796B
CSR Offset
Host Addr
A[11:0]
SD[15:8]
SD[7:0]
AX88796B
CSR Offset
0
Offset 1
Offset 0
0
0
no effect
To Offset 0
0
2
Offset 1
Offset 1
1
2
no effect
To Offset 1
1
4
Offset 3
Offset 2
2
4
no effect
To Offset 2
2
6
Offset 3
Offset 3
3
6
no effect
To Offset 3
3
8
Offset 5
Offset 4
4
8
no effect
To Offset 4
4
A
Offset 5
Offset 5
5
A
no effect
To Offset 5
5
C
Offset 7
Offset 6
6
C
no effect
To Offset 6
6
E
Offset 7
Offset 7
7
E
no effect
To Offset 7
7
10
Offset 9
Offset 8
8
10
no effect
To Offset 8
8
12
Offset 9
Offset 9
9
12
no effect
To Offset 9
9
14
Offset B
Offset A
A
14
no effect
To Offset A
A
16
Offset B
Offset B
B
16
no effect
To Offset B
B
18
Offset D
Offset C
C
18
no effect
To Offset C
C
1A
Offset D
Offset D
D
1A
no effect
To Offset D
D
1C
Offset F
Offset E
E
1C
no effect
To Offset E
E
1E
Offset F
Offset F
F
1E
no effect
To Offset F
F
20
10 (DP)
10 (DP)
10 (DP)
20
10 (DP)
10 (DP)
10 (DP)
22
X
X
X
22
X
X
X
24
Offset 13
Offset 12
12
24
no effect
To Offset 12
12
26
Offset 13
Offset 13
13
26
no effect
To Offset 13
13
28
Offset 15
Offset 14
14
28
no effect
To Offset 14
14
2A
Offset 15
Offset 15
15
2A
no effect
To Offset 15
15
2C
Offset 17
Offset 16
16
2C
no effect
To Offset 16
16
2E
Offset 17
Offset 17
17
2E
no effect
To Offset 17
17
A0
A1
A2
A3
A4
A5/FIFO_SEL
CSn
RDn
WRn
IRQ
AEN/PSEN
A0
A1
A2
A3
A4
A5
A11
CSn
RDn
WRn
INT
Samsung2440
AX88796B



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