TMP86CS25AFG datasheet(90/194 Pages) TOSHIBA

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Page 80

8. 18-Bit Timer/Counter (TC1)

8.3 Function

TMP86CS25AFG

8.3.4 Frequency Measurement mode

In this mode, the frequency of ECIN pin input pulse is measured. When using this mode, set

TC1CR1<TC1CK> to the external clock.

The edge of the ECIN input pulse is counted during “H” level of the window gate pulse selected by

TC1CR2<SGP>. To use ECNT input as a window gate pulse, TC1CR2<SGP> should be set to “00”.

An INTTC1 interrupt is generated on the falling edge or both the rising/falling edges of the window gate

pulse, that can be selected by TC1CR2<SGEDG>. In the interrupt service program, read the contents of

TREG1A while the count is stopped (window gate pulse is low), then clear the counter using

TC1CR1<TC1C>. When the counter is not cleared, counting up resumes from previous stopping value.

The window pulse status can be monitored by TC1SR<HECF>.

When up counter is counted up from 3FFFFH to 00000H, an overflow occurs. At that time,

TC1SR<HEOVF> is set to “1”. TC1SR<HEOVF> remains the previous data until the counter is required to be

cleared by TC1CR1<TC1C>.

Using TC6 output (PWM6/PDO6/PPG6) for the window gate pulse, external output of PWM6/PDO6/PPG6 to

MUL3 pin can be controlled using TC1CR2<TC6OUT>. Zero-clearing TC1CR2<TC6OUT> outputs PWM6/

PDO6

/PPG6 to MUL3 pin; setting 1 in TC1CR2<TC6OUT> does not output PWM6/PDO6/PPG6 to MUL3 pin.

(TC1CR2<TC6OUT> is used to control output to MUL3 pin only. Thus, use the timer counter 6 control regis-

ter to operate/stop PWM6/PDO6/PPG6.)

When the internal window gate pulse is selected, the window gate pulse is set as follows.

The internal window gate pulse consists of “H” level period (Ta) that is counting time and “L” level period

(Tb) that is counting stop time. Ta or Tb can be individually set by TREG1B. One cycle contains Ta + Tb.

Note 1: Because the internal window gate pulse is generated in synchronization with the internal divider, it may be

delayed for a maximum of one cycle of the source clock (WGPSCK) immediately after start of the timer.

Note 2: Set the internal window gate pulse when the timer counter is not operating or during the Tb period. When

Tb is overwritten during the Tb period, the update is valid from the next Tb period.

Note 3: Because the up counter is counted on the falling edge of logical AND-ed pulse (between ECIN pin input and

window gate pulse), if window gate pulse becomes falling edge while ECIN input is "H" level, the up

counter stops plus "1". Therefore, if ECIN input is always "H" level, count value becomes "1".

Table 8-2 Internal window gate pulse setting time

WGPSCK

NORMAL1/2,IDLE1/2 modes

SLOW1/2,

SLEEP1/2 modes

R/W

DV7CK=0

DV7CK=1

Setting "H" level period of the window

gate pulse

(16 - Ta)

× 212/fc

(16 - Ta)

× 213/fc

(16 - Ta)

× 214/fc

(16 - Ta)

× 24/fs

(16 - Ta)

× 25/fs

(16 - Ta)

× 26/fs

(16 - Ta)

× 24/fs

(16 - Ta)

× 25/fs

(16 - Ta)

× 26/fs

Setting "L" level period of the window

gate pulse

(16 - Tb)

× 212/fc

(16 - Tb)

× 213/fc

(16 - Tb)

× 214/fc

(16 - Tb)

× 24/fs

(16 - Tb)

× 25/fs

(16 - Tb)

× 26/fs

(16 - Tb)

× 24/fs

(16 - Tb)

× 25/fs

(16 - Tb)

× 26/fs

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