TMP86CS25AFG datasheet(64/194 Pages) TOSHIBA

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Page 54

5. I/O Ports

5.1 Port P1 (P17 to P10)

TMP86CS25AFG

5.1 Port P1 (P17 to P10)

Port P1 is an 8-bit input/output port which is also used as an external interrupt input, serial interface input/output,

UART input/output and segment output of LCD. When used as a segment pins of LCD, the respective bit of P1LCR

should be set to “1”.

When used as an input port or a secondary function (except for segment) pins, the respective output latch (P1DR)

should be set to “1” and its corresponding P1LCR bit should be set to “0”. When used as an output port, the respec-

tive P1LCR bit should be set to “0”. During reset, the output latch is initialized to “1”.

P1 port output latch (P1DR) and P1 port terminal input (P1PRD) are located on their respective address.

When read the output latch data, the P1DR should be read and when read the terminal input data, the P1PRD reg-

ister should be read.

If the terminal input data which is configured as LCD segment output is read, unstable data is read.

Figure 5-2 Port 1

Note: With ports assigned as MUL6 to MUL0, assigned pins can be switched by the multi function register (MULSEL). The

assigned functions are shown in “5.7 Multi Function Register”.

P1DR

(0001H)

R/W

543

P17

SEG59

SCK0

P16

SEG58

TxD

SO0

P15

SEG57

RxD

SI0

P14

SEG56

MUL6

P13

SEG55

MUL5

P12

SEG54

MUL4

P11

SEG53

P10

SEG52

(Initial value: 1111 1111)

P1LCR

(0029H)

543

(Initial value: 0000 0000)

P1LCR

Port P1/segment output select

(set for each bit individually)

0: P1 input/output port or secondary function (expect for segment)

1: segment output

R/W

P1PRD

(0008H)

Read only

543

P17

P16

P15

P14

P13

P12

P11

P10

Output latch

P1LCRi

Data output (P1DR)

Output latch data (P1DR)

LCD data output

Control input

Terminal input (P1PRD)

STOP

OUTEN

Control output

P1LCRi input

P1i

Note: i = 7 to 0

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