TMP86CS25AFG datasheet(66/194 Pages) TOSHIBA

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Page 56

5. I/O Ports

5.3 Port P3 (P36 to P30)

TMP86CS25AFG

5.3 Port P3 (P36 to P30)

Port P3 is a 7-bit input/output port.

It is also used as a External interrupt input, timer/counter input/output, divider output and LCD common/segment

output.

When used as an input port or a secondary function pins, after setting segment/common output control (P3LCR) to

“0” respective output latch (P3DR) should be set to “1”. During reset, the P3DR is initialized to “1”, and segment

output control (P3LCR) is initialized by “0”. In using it as LCD segment/ common output, it sets the bit to which

P3LCR corresponds to “1”.

P3 port output latch (P3DR) and P3 port terminal input (P3PRD) are located on their respective address.

When read the output latch data, the P3DR should be read and when read the terminal input data, the P3PRD reg-

ister should be read. If a read instruction is executed for port P3, read data of bit 7 is unstable.

Figure 5-4 Port 3

Note: With ports assigned as MUL6 to MUL0, assigned pins can be switched by the multi function register (MULSEL).

The assigned functions are shown in “5.7 Multi Function Register”.

P3DR

(0003H)

R/W

543

P36

COM7

MUL6

P35

COM6

MUL5

P34

COM5

MUL4

P33

SEG51

MUL3

P32

SEG50

MJUL2

P31

SEG49

MJUL1

P30

SEG48

MJUL0

(Initial value: *111 1111)

P3LCR

(0004H)

543

(Initial value: *000 0000)

P3LCR

Port P3 control

(set for each bit individually)

0: P3 input/output port or function except LCD segment or common output

1: LCD segment output/common output

R/W

P3PRD

(000AH)

Read only

543

P36P35

P34P33

P32P31

P30

Output latch

P3LCRi

Data output (P3DR)

Output latch data (P3DR)

LCD data output

Control input

Terminal input (P3PRD)

STOP

OUTEN

Control output

P3LCRi input

P3i

Note: i = 6 to 0

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