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TMP86CS25AFG bảng dữ liệu(PDF) 85 Page - Toshiba Semiconductor

tên linh kiện TMP86CS25AFG
Giải thích chi tiết về linh kiện  8 Bit Microcontroller
PDF  194 Pages
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nhà sản xuất  TOSHIBA [Toshiba Semiconductor]
Trang chủ  http://www.semicon.toshiba.co.jp/eng
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TMP86CS25AFG bảng dữ liệu(HTML) 85 Page - Toshiba Semiconductor

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TMP86CS25AFG
Note 1: fc; High-frequency clock [Hz] fs; Low-frequency clock [Hz] * ; Don’t care
Note 2: Writing to the low-byte of the timer register 1A (TREG1AL, TREG1AM), the compare function is inhibited until the high-
byte (TREG1AH) is written.
Note 3: Set the mode and source clock, and edge (selection) when the TC1 stops (TC1S=00).
Note 4: “fc” can be selected as the source clock only in the timer mode during SLOW mode and in the pulse width measurement
mode during NORMAL 1/2 or IDLE 1/2 mode.
Note 5: When a read instruction is executed to the timer register (TREG1A), the counter immediate value, not the register set
value, is read out. Therefore it is impossible to read out the written value of TREG1A. To read the counter value, the read
instruction should be executed when the counter stops to avoid reading unstable value.
Note 6: Set the timer register (TREG1A) to
≥1.
Note 7: When using the timer mode and pulse width measurement mode, set TC1CK (TC1 source clock select) to internal clock.
Note 8: When using the event counter mode, set TC1CK (TC1 source clock select) to external clock.
Note 9: Because the read value is different from the written value, do not use read-modify-write instructions to TREG1A.
Note 10:fc/27, fc/23can not be used as source clock in SLOW/SLEEP mode.
Note 11:The read data of bits 7 to 2 in TREG1AH are always “0”. (Data “1” can not be written.)
Timer/counter 1 control register 1
7
6543
210
TC1CR1
(0014H)
TC1C
TC1S
TC1CK
TC1M
(Initial value: 1000 1000)
TC1C
Counter/overfow flag
controll
0:
1:
Clear Counter/overflow flag ( “1” is automatically set after clearing.)
Not clear Counter/overflow flag
R/W
TC1S
TC1 start control
00:
10:
*1:
Stop and counter clear and overflow flag clear
Start
Reserved
R/W
TC1CK
TC1 source clock select
NORMAL1/2,IDLE1/2 modes
SLOW1/2
mode
SLEEP1/2
mode
R/W
DV7CK="0"
DV7CK="1"
000:
001:
010:
011:
100:
101:
110:
fc
fs
fc/223
fc/213
fc/211
fc/27
fc/23
fc
fs
fs/215
fs/25
fs/23
fc/27
fc/23
fc
-
fs/215
fs/25
fs/23
-
-
fc
-
fs/215
fs/25
fs/23
-
-
111:
External clock (ECIN pin input)
TC1M
TC1 mode select
00:
01:
10:
11:
Timer/Event counter mode
Reserved
Pulse width measurement mode
Frequency measurement mode
R/W



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