TMP88CS38FG datasheet(24/226 Pages) TOSHIBA

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TMP88CS38/CM38A/CP38A

2007-09-12

88CS38-24

1. Interrupt master enable flag (IMF)

The interrupt master enable flag (IMF) enables and disables the acceptance of all

maskable interrupts. Clearing this flag to “0” disables the acceptance of all maskable

interrupts. Setting to “1” enables the acceptance of interrupts.

When an interrupt is accepted, this flag is cleared to “0” to temporarily disable the

acceptance of other maskable interrupts. After execution of the interrupt service

program, this flag is set to “1” by the maskable interrupt return instruction [RETI] to

again enable the acceptance of interrupts. If an interrupt request has already been

occurred, interrupt service starts immediately after execution of the [RETI]

instruction.

Pseudo non-maskable interrupts are returned by the [RETN] instruction. In this

case, the IMF is set to “1” only when pseudo non-maskable interrupt service is started

with interrupt acceptance enabled (IMF

= 1). Note that the IMF remains “0” when

cleared by the interrupt service program.

The IMF is assigned to bit0 at address 0003AH in the SFR, and can be read and

written by an instruction. The IMF is normally set and cleared by the [EI] and [DI]

instructions, and the IMF is initialized to “0” during reset.

2. Individual interrupt enable flags (EF17 to EF3)

These flags enable and disable the acceptance of individual maskable interrupts,

except for an external interrupt 0. Setting the corresponding bit of an individual

interrupt enable flag to “1” enables acceptance of an interrupt, setting the bit to “0”

disables acceptance.

Example 1: Sets EF for individual interrupt enable, and sets IMF to “1”.

;

Disable interrupt

(EIRE), 00000001B

;

EF16 ← 1

LDW

(EIRL), 1110100010100001B

EF15 to EF13, EF11, EF7, EF5, IMF ← 1

Example 2: Sets an individual interrupt enable flag to “1”.

SET

(EIRH). 4

;

EF12 ← 1

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