TMP88CS38FG datasheet(92/226 Pages) TOSHIBA

92 / 226 page

TMP88CS38/CM38A/CP38A

2007-09-12

88CS38-92

(3) Serial clock

a. Clock source

The SCK (Bits 2 to 0 in SBICRA) is used to select a maximum transfer

frequency output from the SCL pin in the master mode. Set a communication

baud rate that meets the I2C bus specification, such as the shortest pulse width of

tLOW, based on the equations shown below.

Four or more machine cycles are required for both high and low levels of pulse

width in the external clock which is input from SCL pin.

Note:

Since the I

2C of TMP88CS38 AND TMP88CM38A/CP38A can not be used as

the Fast mode and the High Speed mode, do not set SCK as the frequency

that is over 100 kHz.

This I

2C bus circuit does not support high-speed mode, it supports standard mode only.

Set the baud rates, which have been calculated according to the formula below, to meet

the specifications of the I2C bus, such as the smallest pulse width of tLOW,

Figure 2.9.7 Clock Source

b. Clock synchronization

In the I2C bus mode, in order to drive a bus with a wired AND, a master device

which pulls down a clock pulse to low will, in the first place, invalidate a clock

pulse of another master device which generates a high-level clock pulse.

The serial bus interface circuit has a clock synchronization function. This

function ensures normal transfer even if there are two or more masters on the

same bus.

The example explains clock synchronization procedures when two masters

simultaneously exist on a bus.

Figure 2.9.8 Clock Synchronization

1/fscl

tLOW = 2

n/fc

tHIGH = 2

n/fc

+ 8/fc

fscl

= 1/(tLow + tHIGH)

Note: fc: High-frequency clock

SCK

(Bits 2 to 0 in the SBICRA)

DV1CK

= 0

DV1CK

= 1

000

001

010

011

100

101

110

tHIGH

tLOW

SCL pin (Master 1)

SCL pin (Master 2)

SCL (Bus)

wait

Count start

Count reset

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