TMP88CS38FG datasheet(96/226 Pages) TOSHIBA

96 / 226 page

TMP88CS38/CM38A/CP38A

2007-09-12

88CS38-96

The serial bus interface circuit compares levels of a SDA line of a bus with its those

SDA pin at the rising edge of the SCL line. If the levels are unmatched, arbitration is

lost and the AL (Bit3 in SBISRB) is set to “1”.

When the AL is set to “1”, the MST and TRX are cleared to “0” and the mode is

switched to a slave receiver mode.

The AL is cleared to “0” by writing or reading data to or from the SBIDBR or writing

data to the SBICRB.

Figure 2.9.12 Example of when a Serial Bus Interface Circuit is a Master B

(11) Slave address match detection monitor

In the slave mode, the AAS (Bit2 in SBISR) is set to “1” when the received data is

“GENERAL CALL” or the received data matches the slave address setting by I2CAR

with an address recognition mode (ALS

= 0).

When a serial bus interface circuit operates in the free data format (ALS

= 1), the

AAS is set to “1” after receiving the first 1-word of data.

The AAS is cleared to “0” by writing data to the SBIDBR or reading data from the

SBIDBR.

(12) GENERAL CALL detection monitor

The AD0 (Bit1 in SBISR) is set to “1” when all 8-bit received data is “0” immediately

after a start condition in a slave mode. The AD0 is cleared to “0” when a start or stop

condition is detected on a bus.

(13) Last received bit monitor

The SDA value stored at the rising edge of the SCL is set to the LRB (Bit0 in

SBISRB). In the acknowledge mode, immediately after an INTSBI interrupt request is

generated, an acknowledge signal is read by reading the contents of the LRB.

Releasing SDA pin and SCL pin to high level as losing arbitration.

D7A

D6A

D5A

D4A

D3A

D2A

D1A

D0A

D7A’

D6A’

D5A’

D7B

D6B

SCL pin

SDA pin

SCL pin

SDA pin

MST

TRX

Accessed to

SBIDBR or SBICRB

Master

789

Stop clock output

INTSBI

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