TMP88CS38 datasheet(23/226 Pages) TOSHIBA

23 / 226 page

TMP88CS38/CM38A/CP38A

2007-09-12

88CS38-23

Interrupt latches (IL) that hold the interrupt requests are provided for interrupt sources.

Each interrupt vector is independent.

The interrupt latch is set to “1” when an interrupt request is generated, and requests the

CPU to accept the interrupt. The acceptance of maskable interrupts can be selectively enabled

and disabled by program using the interrupt master enable flag (IMF) and the individual

interrupt enable flags (EF). When two or more interrupts are generated simultaneously, the

interrupt is accepted in the highest priority order as determined by the hardware. Figure 1.5.1

shows the interrupt controller.

(1) Interrupt latches (IL31 to IL2)

Interrupt latches are provided for each source, except for a software interrupt. The latch

is set to “1” when an interrupt request is generated, and requests the CPU to accept the

interrupt. The latch is cleared to “0” just after the interrupt is accepted. All interrupt

latches are initialized to “0” during reset.

The interrupt latches are assigned to addresses 0003CH, 0003DH, 0002EH and 0002FH

in the SFR. Except for IL2, each latch can be cleared to “0” individually by an instruction ;

however, the read-modify-write instruction such as bit manipulation or operation

instructions cannot be used. When interrupt occurred during order execution, the reason is

because interrupt request is cleared. Thus, interrupt requests can be canceled and

initialized by the program. Note that request the interrupt latches cannot be set to “1” by

an instruction. For example, it may be that each latch is cleared even if an interrupt

request is generated during instruction exection.

The contents of interrupt latches can be read out by an instruction. Therefore, testing

interrupt request by software is possible.

Example 1: Clears interrupt latches

;

Disable interrupt

LDW

(ILL), 1110100000111111B

;

IL12, IL10 to IL6 ← 0

Example 2: Reads interrupt latches

WA, (ILL)

;

← ILH, A ← ILL

Example 3: Tests an interrupt latch

TEST

(ILL). 7

;

if IL7 = 1 then jump

F, SSET

(2) Interrupt enable register (EIR)

The interrupt enable register (EIR) enables and disables the acceptance of interrupts,

except for the pseudo non-maskable interrupts (Software and watchdog timer interrupts).

Pseudo non-maskable interrupts are accepted regardless of the contents of the EIR;

however, the pseudo non-maskable interrupt cannot be nested more than once at the same

time.

The EIR consists of an interrupt master enable flag (IMF) and the individual interrupt

enable flags (EF). These registers are assigned to addresses 0003AH, 0003BH, 0002CH and

0002DH in the SFR, and can be read and written by an instruction (including

read-modify-write instruction such as bit manipulation instructions).

Note:

Do not use the read-modify-write instruction for the EIRL (Address 0003AH) during

pseudo non-maskable interrupt service task. If the read-modify-write instruction is used,

the IMF is not set to “1” after RETN.

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