TMP88CS38 datasheet(59/226 Pages) TOSHIBA

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TMP88CS38/CM38A/CP38A

2007-09-12

88CS38-59

(2) Watchdog timer enable

The watchdog timer is enabled by setting WDTEN (Bit3 in WDTCR1) to “1”.

WDTEN is initialized to “1” during reset, so the watchdog timer operates immediately

after reset is released.

Example: Disables watchdog timer

LDW

(WDTCR1), 00001000B

;

WDTEN

← 1

(3) Watchdog timer disable

To disable the watchdog timer, clear the interrupt mask enable flag (IMF) to “0” and

write the clear code (4EH) into WDTCR2. Then, clear WDTEN (Bit3 in WDTCR1) to “0”.

When WDTEN is “0”, the watchdog timer is disabled by writing the disable code (B1H)

into WDTCR2. If WDTEN is cleared to “0” after the disable code has been written into

WDTCR2, the watchdog timer is not disabled. While it is disabled, its binary counter is

cleared.

Example:

;

Disables interrupt acceptance.

(WDTCR2), 4EH

;

Clears the watchdog timer.

LDW

(WDTCR1), B101H

;

Disables the watchdog timer.

;

Enables interrupt acceptance.

Table 2.4.1 Watchdog Timer Detection Time (Example: fc

= 16 MHz)

Watchdog timer detection time [s]

NORMAL mode

WDTT

DV1CK

= 0

DV1CK

= 1

2.097

4.194

524.288 m

1.048

131.072 m

262.1

32.768 m

65.5

2.4.3

Watchdog Timer Interrupt (INTWDT)

This is a pseudo non-maskable interrupt which can be accepted regardless of the

contents of the EIR. If a watchdog timer interrupt or a software interrupt is already

accepted, however, the new watchdog timer interrupt waits until the previous interrupt

processing is completed (the end of the [RETN] instruction execution).

The stack pointer (SP) should be initialized before using the watchdog timer output as an

interrupt source with WDTOUT.

Example: Watchdog timer interrupt setting up

SP, 023FH

;

Sets the stack pointer

(WDTCR1), 00001000B

;

WDTOUT

← 0

2.4.4

Watchdog Timer Reset

If the watchdog timer output becomes active, a reset is generated, which drivers the

RESET

pin (Sink open drain input/output with pull-up) low to reset the internal hardware.

The reset output time is about 8/fc to 24/fc [s] (0.5 to 1.5

μs at fc = 16.0 MHz).

Note:

If there is any fluctuation in the oscillation frequency at the start of clock oscillation, the

reset time includes error. Thus, regard the reset time as an approximate value.

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