TMP88CS38 datasheet(93/226 Pages) TOSHIBA

93 / 226 page

TMP88CS38/CM38A/CP38A

2007-09-12

88CS38-93

As master 1 pulls down the SCL pin to the low level at point “a”, the SCL line of

the bus becomes the low level. After detecting this situation, master 2 resets

counting a clock pulse in the high level and sets the SCL pin to the low level.

Master 1 finishes counting a clock pulse in the low level at point “b” and sets the

SCL pin to the high level. Since master 2 holds the SCL line of the bus at the low

level, master 1 waits for counting a clock pulse in the high level. After master 2

sets a clock pulse to the high level at point “c” and detects the SCL line of the bus

at the high level, master 1 starts counting a clock pulse in the high level. Then,

the master, which has finished the counting a clock pulse in the high level, pulls

down the SCL pin to the low level.

The clock pulse on the bus is deteminded by the master device with the shortest

high-level period and the master device with the longest low-level period from

among those master devices connected to the bus.

(4) Slave address and address recognition mode specification

When the serial bus interface circuit is used with an addressing format to recognize

the slave address, clear the ALS (Bit0 in I2CAR) to “0”, and set the SA (Bits 7 to 1 in

I2CAR) to the slave address.

When the serial bus interfac circuit is used with a free data format not to recognize

the slave address, set the ALS to “1”. With a free data format, the slave address and the

direction bit are not recognized, and they are processed as data from immediately after

start condition.

(5) Master/slave selection

To set a master device, the MST (Bit7 in SBICRB) should be set to “1”. To set a slave

device, the MST should be cleared to “0”.

When a stop condition on the bus or an arbitration lost is detected, the MST is

cleared to “0” by the hardware.

(6) Transmitter/receiver selection

To set the device as a transmitter, the TRX (Bit6 in SBICRB) should be set to “1”. To

set the device as a receiver, the TRX should be cleared to “0”. When data with an

addressing format is transferred in the slave mode, the TRX is set to “1” by a hardware

if the direction bit (R/ W ) sent from the master device is “1”, and is cleared to “0” by a

hardware if the bit is “0. In the master mode, after an acknowledge signal is returned

from the slave device, the TRX is cleared to “0” by a hardware if a transmitted direction

bit is “1”, and is set to “1” by a hardware if it is “0”. When an acknowledge signal is not

returned, the current condition is maintained.

When a stop condition on the bus or an arbitration lost is detected, the TRX is

cleared to “0” by the hardware. The following table show TRX changing conditions in

each mode and TRX value after changing.

Mode

Direction Bit

Conditions

TRX after Changing

“0”

Slave

mode

“1”

A received slave address is the

same value set to I2CAR

“1”

“0”

“1”

Master

mode

“1”

ACK signal is returned

“0”

When a serial bus interface circuit operates in the free data format, a slave address

and a direction bit are not recognized. They are handled as data just after generating a

start condition. The TRX is not changed by a hardware.

TMP88CS38 bảng dữ liệu(PDF) 93 Page - Toshiba Semiconductor

TMP88CS38 bảng dữ liệu(HTML) 93 Page - Toshiba Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL