TMP91CW60DFG datasheet(39/262 Pages) TOSHIBA

39 / 262 page

Page 36

2007-12-03

TMP91CW60

3.2.4

Detailed Description of the Transfer Mode Register

Note 1: “n” is the corresponding micro DMA channels 0 to 3.

DMADn+/DMASn+: Post-increment (Increment register value after transfer)

DMADn-/DMASn-: Post-decrement (Decrement register value after transfer)

The I/Os in the table mean fixed address and the memory means increment (INC) or decrement (DEC)

addresses.

Note 2: Execution time is under the condition of:

16-bit bus width (Both transfer and destination address area)/0 waits/

fc = 20 MHz/selected high-frequency mode (fc

× 1)

Note 3: Do not use an undefined code for the transfer mode register except for the defined codes listed in the

above table.

(DMAM0 to DMAM3)

Mode

Note: The upper three bit of data programmed to these registers must always be 0.

Transfer destination address INC mode・・・・・・・・・・I/O to memory

(DMADn+)

← (DMASn)

DMACn

← DMACn − 1

if DMACn = 0 then INTTC is generated

8 states (800 ns)

@ byte/word transfer

12 states (1200 ns)

@ 4-byte/word transfer

Transfer destination address DEC mode ・・・・・・・・・I/O to memory

(DMADn-)

← (DMASn)

DMACn

← DMACn − 1

if DMACn = 0 then INTTC is generated

8 states (800 ns)

@ byte/word transfer

12 states (1200 ns)

@ 4-byte/word transfer

Transfer source address INT mode・・・・・・・・・・・・memory to I/O

(DMADn)

← (DMASn+)

DMACn

← DMACn − 1

if DMACn = 0 then INTTC is generated

8 states (800 ns)

@ byte/word transfer

12 states (1200 ns)

@ 4-byte/word transfer

Transfer source address DEC mode ・・・・・・・・・・・memory to I/O

(DMADn)

← (DMASn-)

DMACn

← DMACn − 1

if DMACn = 0 then INTTC is generated

8 states (800 ns)

@ byte/word transfer

12 states (1200 ns)

@ 4-byte/word transfer

Address fixed mode・・・・・・・・・・・・・・・・・・・・・I/O to I/O

(DMADn)

← (DMASn)

DMACn

← DMACn − 1

if DMACn = 0 then INTTC is generated

8 states (800 ns)

@ byte/word transfer

12 states (1200 ns)

@ 4-byte/word transfer

010

Counter mode for counting number of times interrupt is generated

DMASn

← DMASn + 1

DMACn

← DMACn − 1

if DMACn = 0 then INTTC is generated

5 states

(500 ns)

Execution time

ZZ: 0 = Byte transfer, 1 = Word transfer, 2 = 4-byte transfer, 3 = Reserved

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