RT9245C

20

DS9245C-02 March 2007

www.richtek.com

Design Procedure Suggestion

a.Output filter pole and zero (Inductor, output capacitor

value & ESR).

b.Error amplifier compensation & sawtooth wave amp-

litude (compensation network).

Current Loop Setting

a.GM amplifier S/H current (current sense component

DCR, CSN pin external resistor value).

VRM Load Line Setting

a.Droop amplitude (ADJ pin resistor).

c.DAC offset voltage setting (VOSS pin & compen- sation

network resistor RB1).

Power Sequence & SS

DVD pin external resistor and SS pin capacitor.

PCB Layout

a.Kelvin sense for current sense GM amplifier input.

b.Refer to layout guide for other items.

Voltage Loop Setting

Design Example

Given :

Apply for four phase converter

Ω Load Line)

OCP trip point set at 40A for each channel (S/H)

DCR = 1m

Ω of inductor at 25°C

L = 0.3

μH

μF with 1mΩ equivalent ESR.

Figure 27. EA Frequency Response with closed loop gain set at 0db to observe gain-bandwidth product; -3dB at

10.86MHz

0dB

180

°