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RT9245CPC bảng dữ liệu(PDF) 17 Page - Richtek Technology Corporation

tên linh kiện RT9245CPC
Giải thích chi tiết về linh kiện  Multi-Phase PWM Controller for CPU Core Power Supply
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nhà sản xuất  RICHTEK [Richtek Technology Corporation]
Trang chủ  http://www.richtek.com
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RT9245C
17
DS9245C-02 March 2007
www.richtek.com
VID on the Fly
With external pull up resistors tied to VID pins, RT9245C
converters different VID codes from CPU into output
voltage. Figure 16 and Figure 17 show the waveforms of
VID on the fly function.
Load Line Setting and Thermal Compensation
VADJ = 8 x AVG(IX) x RADJ
VOUT = VDAC - VADJ
AVG(IX) is a PTC current. By properly use an NTC resistor
at ADJ. Load line can be thermally compensated.
Figure 17
Output Voltage Offset Function
To meet Intel® requirement of initial offset of load line,
RT9245C provides programmable initial offset function.
External resistor RVOSS and voltage source at VOSS pin
generate offset current
, where VVOSS is 1V typical. One quarter of IVOSS flows
through RB1 as shown in Figure 18. Error amplifier would
hold the inverting pin equal to VDAC - VADJ. Thus output
voltage is subtracted from VDAC - VADJ for a constant offset
voltage.
A positive output voltage offset is possible by connecting
RVOSS to VDD instead of to GND. Please note that when
RVOSS is connected to VDD, VVOSS is VDD
− 2V typically
and half of IVOSS flows through RFB1. VCORE is rewritten as:
VOSS
VOSS
VOSS
V
I=
R
×
FB1
CORE
DAC
ADJ
VOSS
R
V= V
- V
-
4R
VOSS
FB1
ADJ
DAC
CORE
R
R
V
-
V
V
+
=
Figure 19
Voltage Offset Function
1.268
1.27
1.272
1.274
1.276
1.278
1.28
1.282
1.284
50
60
70
80
90
100
110
ROSS (k )
(k
Ω)
Figure 18. Offset Setting
+
-
EA
1/4 IVOSS
RB1
VDAC-VADJ
Figure 16
CH1:(5V/Div)
CH2:(500mV/Div)
CH3:(500mV/Div)
CH4:(1V/Div)
VID on the Fly (Falling)
Time (25
μs/Div)
VCORE
PWM
VFB
VID125
VDAC = 1.500, IOUT = 5A
CH1:(5V/Div)
CH2:(500mV/Div)
CH3:(500mV/Div)
CH4:(1V/Div)
VID on the Fly (Rising)
Time (25
μs/Div)
VCORE
PWM
VFB
VID125
VDAC = 1.500, IOUT = 5A



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