MPC8280 datasheet(375/1386 Pages) FREESCALE

tên linh kiện	MPC8280

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375 / 1386 page

PCI Bridge

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

9-67

The interrupt to the local processor is cleared by setting the appropriate bit in the inbound message

interrupt status register. The interrupt to PCI (INTA) is cleared by setting the appropriate bit in the

outbound interrupt status register.

9.12.1.1

Inbound Message Registers (IMR

The inbound message registers, described in Figure 9-60 and Figure 9-46, are accessible from the PCI bus

and the 60x bus in both host and agent modes.

Figure 9-60. Inbound Message Registers (IMR

9.12.1.2

Outbound Message Registers (OMR

The outbound message registers, described in Figure 9-61 and Figure 9-47, are accessible from the PCI

bus and the 60x bus in both host and agent modes.

Field

IMSG

Reset

Undefined

R/W

Addr

0x10452 (IMR0); 0x10456 (IMR1)

Field

IMSG

Reset

Undefined

R/W

Addr

0x10450 (IMR0); 0x10454 (IMR1)

Table 9-46. IMR

x Field Descriptions

Bits

Name

Description

31–0

IMSG

Inbound message

x. Contains generic data to be passed between the local

processor and external hosts.

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