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MPC8280 bảng dữ liệu(PDF) 379 Page - Freescale Semiconductor, Inc |
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MPC8280 bảng dữ liệu(HTML) 379 Page - Freescale Semiconductor, Inc |
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379 / 1386 page  PCI Bridge MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 9-71 Figure 9-64. I2O Message Queue I2O defines extensions for the PCI bus hardware through which message queues are managed in hardware. 9.12.3.1 PCI Configuration Identification A host identifies an IOP by its PCI class code. When I2O is enabled, configuration information is provided through the PCI configuration space to the host. Refer to the following: • Section 9.11.2.6, “PCI Bus Programming Interface Register” • Section 9.11.2.7, “Subclass Code Register” • Section 9.11.2.8, “PCI Bus Base Class Code Register” 9.12.3.2 Inbound FIFOs The inbound FIFO allows external PCI masters to post messages to the local processor. I2O defines two inbound FIFOs—an inbound post FIFO and an inbound free FIFO. MFA MFA MFA MFA MFA MFA MFA MFA MFA MFA MFA MFA MFA MFA MFA MFA Message frame Message frame Message frame Message frame Message frame Message frame Message frame Message frame Message frame Message frame Message frame Message frame Message frame Message frame Message frame Message frame Inbound free list FIFO Inbound post list FIFO Outbound post list FIFO Outbound free list FIFO Head pointer Tail pointer Local processor write PCI master read PCI master write Local processor read Local processor read Local processor write PCI master write PCI master read Outbound Tail pointer Tail pointer Tail pointer Head pointer Head pointer Head pointer Local memory queue port Inbound queue port |
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