405EX datasheet(63/67 Pages) AMCC

63 / 67 page

PPC405EX – PowerPC 405EX Embedded Processor

Revision 1.09 - August 21, 2007

AMCC Proprietary

Preliminary Data Sheet

In the following example, the data strobes (DQS) and the data are shown to be coincident. There is actually a slight

skew as specified by the SDRAM specifications, and there can be additional skew due to loading and signal

routing. It is recommended that the signal length for all of the DQS signals be matched.

The following example shows the timing relationship between SDRAM DDR Data at the input pin and storing the

data in Stage 1.

Table 24. I/O Timing—DDR SDRAM Read Timing TSD and THD

1. TSD and THD are measured under worst case conditions.

2. Clock speed for the values in the table is 200MHz.

3. The time values in the table include 1/4 of a cycle at 200MHz (5ns x 0.25 = 1.25 ns).

4. To obtain adjusted TSD and THD values for lower clock frequencies, subtract 0.75 ns from the values in the table and add 1/4

of the cycle time for the lower clock frequency (e.g., TSD - 1.25 + 0.25TCYC).

Signal Names

Reference Signal

Read Data vs DQS Set up

TSD (ns)

Read Data vs DQS Hold

THD (ns)

MemData00:07

DQS0

0.35

0.45

MemData08:15

DQS1

0.35

0.45

MemData16:23

DQS2

0.35

0.45

MemData24:31

DQS3

0.35

0.45

ECC0:7

DQS4

0.35

0.45

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